8.2.1.2.3 Thermal Performance

The datasheet-specified junction-to-ambient thermal resistance, R_θJA, is primarily useful for comparing various drivers or approximating thermal performance. However, the actual system performance may be better or worse than this value depending on PCB stackup, routing, number of vias, and copper area around the thermal pad. The length of time the driver drives a particular current will also impact power dissipation and thermal performance. This section considers how to design for steady-state and transient thermal conditions.

The data in this section was simulated using the following criteria:

• 2-layer PCB, standard FR4, 1-oz (35 mm copper thickness) or 2-oz copper thickness.

• Top layer: DRV887x HTSSOP package footprint and copper plane heatsink. Top layer copper area is varied in simulation.
• Bottom layer: ground plane thermally connected through vias under the thermal pad for DRV887x. Bottom layer copper area varies with top copper area. Thermal vias are only present under the thermal pad (grid pattern with 1.2mm spacing).

• 4-layer PCB, standard FR4. Outer planes are 1-oz (35 mm copper thickness) or 2-oz copper thickness.

• Top layer: DRV887x HTSSOP package footprint and copper plane heatsink. Top layer copper area is varied in simulation. Inner planes were kept at 1-oz.
• Mid layer 1: GND plane thermally connected to DRV887x thermal pad through vias. The area of the ground plane is 74.2 mm x 74.2 mm.
• Mid layer 2: power plane, no thermal connection.
• Bottom layer: signal layer with small copper pad underneath DRV887x and thermally connected through via stitching from the TOP and internal GND planes. Bottom layer thermal pad is the same size as the package (5 mm x 4.4 mm). Bottom pad size remains constant as top copper plane is varied. Thermal vias are only present under the thermal pad (grid pattern with 1.2mm spacing).

Figure 20 shows an example of the simulated board for the HTSSOP package. Table 9 shows the dimensions of the board that were varied for each simulation.

Figure 20. HTSSOP PCB model top layer