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SLVSF66A August 2019 – December 2019 DRV8874

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

PWP|16
- MPDS371C

散熱焊盤機械數據 (封裝 | 引腳)

PWP|16
- PPTD312C

訂購信息

6.5 Electrical Characteristics

4.5 V ≤ V_VM ≤ 37 V, –40°C ≤ T_J≤ 150°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER SUPPLIES (VCP, VM)
I_VMQ	VM sleep mode current	V_VM = 24 V, nSLEEP = 0 V, T_J = 25°C		0.75	1	µA
I_VMQ	VM sleep mode current	nSLEEP = 0 V			5	µA
I_VM	VM active mode current	V_VM = 24 V, nSLEEP = 5 V, EN/IN1 = PH/IN2 = 0 V		3	7	mA
t_WAKE	Turnon time	V_VM > V_UVLO, nSLEEP = 5 V to active			1	ms
t_SLEEP	Turnoff time	nSLEEP = 0 V to sleep mode			1	ms
V_VCP	Charge pump regulator voltage	VCP with respect to VM, V_VM = 24 V		5		V
f_VCP	Charge pump switching frequency			400		kHz
LOGIC-LEVEL INPUTS (EN/IN1, PH/IN2, nSLEEP)
V_IL	Input logic low voltage	V_VM < 5 V	0		0.7	V
V_IL	Input logic low voltage	V_VM ≥ 5 V	0		0.8	V
V_IH	Input logic high voltage		1.5		5.5	V
V_HYS	Input hysteresis			200		mV
V_HYS	Input hysteresis	nSLEEP		50		mV
I_IL	Input logic low current	V_I = 0 V	–5		5	µA
I_IH	Input logic high current	V_I = 5 V		50	75	µA
R_PD	Input pulldown resistance	To GND		100		kΩ
TRI-LEVEL INPUTS (PMODE)
V_TIL	Tri-level input logic low voltage		0		0.65	V
V_TIZ	Tri-level input Hi-Z voltage		0.9	1.1	1.2	V
V_TIH	Tri-level input logic high voltage		1.5		5.5	V
I_TIL	Tri-level input logic low current	V_I = 0 V	–50	–32		µA
I_TIZ	Tri-level input Hi-Z current	V_I = 1.1 V	–10		10	µA
I_TIH	Tri-level input logic high current	V_I = 5 V		113	150	µA
R_TPD	Tri-level pulldown resistance	To GND		44		kΩ
R_TPU	Tri-level pullup resistance	To internal 5 V		156		kΩ
QUAD-LEVEL INPUTS (IMODE)
V_QI2	Quad-level input level 1	Voltage to set quad-level 1	0		0.45	V
R_QI2	Quad-level input level 2	Resistance to GND to set quad-level 2	18.6	20	21.4	kΩ
R_QI3	Quad-level input level 3	Resistance to GND to set quad-level 3	57.6	62	66.4	kΩ
V_QI4	Quad-level input level 4	Voltage to set quad-level 4	2.5		5.5	V
R_QPD	Quad-level pulldown resistance	To GND		136		kΩ
R_QPU	Quad-level pullup resistance	To internal 5 V		68		kΩ
OPEN-DRAIN OUTPUTS (nFAULT)
V_OL	Output logic low voltage	I_OD = 5 mA			0.3	V
I_OZ	Output logic high current	V_OD = 5 V	–2		2	µA
DRIVER OUTPUTS (OUT1, OUT2)
R_{DS(on)_HS}	High-side MOSFET on resistance	V_VM = 24 V, I_O = 2 A, T_J = 25°C		100	120	mΩ
R_{DS(on)_LS}	Low-side MOSFET on resistance	V_VM = 24 V, I_O = –2 A, T_J = 25°C		100	120	mΩ
V_SD	Body diode forward voltage	I_SD = 1 A		0.9		V
t_RISE	Output rise time	V_VM = 24 V, OUTx rising 10% to 90%		150		ns
t_FALL	Output fall time	V_VM = 24 V, OUTx falling 90% to 10%		150		ns
t_PD	Input to output propagation delay	EN/IN1, PH/IN2 to OUTx, 200 Ω from OUTx to GND		400		ns
t_DEAD	Output dead time	Body diode conducting		100		ns
CURRENT SENSE AND REGULATION (IPROPI, VREF)
A_IPROPI	Current mirror scaling factor			450		µA/A
A_ERR⁽¹⁾	Current mirror scaling error	I_OUT < 0.4 A 5.5 V ≤ V_VM ≤ 37 V	–30		30	mA
		0.4 A ≤ I_OUT < 1 A 5.5 V ≤ V_VM ≤ 37 V	–7.5		7.5	%
		1 A ≤ I_OUT < 2 A 5.5 V ≤ V_VM ≤ 37 V	–6		6
		2 A ≤ I_OUT ≤ 4 A 5.5 V ≤ V_VM ≤ 37 V	–5.5		5.5
t_OFF	Current regulation off time			25		µs
t_DELAY	Current sense delay time			1.6		µs
t_DEG	Current regulation deglitch time			0.6		µs
t_BLK	Current regulation blanking time			1.1		µs
PROTECTION CIRCUITS
V_UVLO	Supply undervoltage lockout (UVLO)	V_VM rising	4.3	4.45	4.6	V
V_UVLO	Supply undervoltage lockout (UVLO)	V_VM falling	4.2	4.35	4.5	V
V_{UVLO_HYS}	Supply UVLO hysteresis			100		mV
t_UVLO	Supply undervoltage deglitch time			10		µs
V_CPUV	Charge pump undervoltage lockout	VCP with respect to VM, V_VCP falling		2.25		V
I_OCP	Overcurrent protection trip point		6	10		A
t_OCP	Overcurrent protection deglitch time			3		µs
t_RETRY	Overcurrent protection retry time			2		ms
T_TSD	Thermal shutdown temperature		160	175	190	°C
T_HYS	Thermal shutdown hysteresis			20		°C

(1) At low currents, the IPROPI output has a fixed offset error with respect to the I_OUT current through the low-side power MOSFETs.

Figure 1. Timing Parameter Diagram