ZHCSIO5B October 2017 – January 2021 DRV8873-Q1
PRODUCTION DATA
| PIN | TYPE(4) | DESCRIPTION | ||
|---|---|---|---|---|
| NAME | NO. | |||
| DRV8873H-Q1 | DRV8873S-Q1 | |||
| CPH | 22 | 22 | PWR | Charge pump switching node. Connect a X7R capacitor with a value of 47 nF between the CPH and CPL pins. |
| CPL | 23 | 23 | PWR | Charge pump switching node. Connect a X7R capacitor with a value of 47 nF between the CPH and CPL pins. |
| DVDD | 1 | 1 | PWR | Digital regulator. This pin is the 5-V internal digital-supply regulator. Bypass this pin to GND with a 6.3-V, 1-μF ceramic capacitor. |
| EN/IN1 | 7 | 7 | I | Control Inputs. For details, see the Section 7.3.1.1 section. This pin has an internal pulldown resistor to GND. |
| DISABLE | 9 | 9 | I | Bridge disable input. A logic high on this pin disables the H-bridge Hi-Z. Internal pullup to DVDD. |
| GND | 24 | 24 | PWR | Ground pin |
| IPROPI1 | 10 | 10 | O | High-side FET current. The analog current proportional to the current flowing in the half bridge. |
| IPROPI2 | 12 | 12 | O | High-side FET current. The analog current proportional to the current flowing in the half bridge. |
| nITRIP | 5 | — | I | Internal current-regulation control pin (ITRIP). To enable the ITRIP feature, do not connect this pin (or tie it to GND). To disable the ITRIP feature, connect this pin to the DVDD pin. |
| nOL | 6 | — | I | Open-load diagnostic control pin. To run the open-load diagnostic at power up, tie it to ground. Connect it to DVDD, open-load diagnostic will be disabled. |
| MODE | 3 | — | I | Input mode pin. Sets the PH/EN, PWM, or independent-PWM mode. |
| OUT1 | 18 | 18 | O | Half-bridge output 1. Connect this pin to the motor or load. |
| OUT1 | 19 | 19 | O | Half-bridge output 1. Connect this pin to the motor or load. |
| OUT2 | 14 | 14 | O | Half-bridge output 2. Connect this pin to the motor or load. |
| OUT2 | 15 | 15 | O | Half-bridge output 2. Connect this pin to the motor or load. |
| PH/IN2 | 8 | 8 | I | Control inputs. For details, see the Section 7.3.1.1 section. This pin has an internal pulldown resistor to GND. |
| SCLK | — | 5 | I | Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin. |
| SDI | — | 4 | I | Serial data input. Data is captured on the falling edge of the SCLK pin. |
| SDO | — | 3 | PP | Serial data output. Data is shifted out on the rising edge of the SCLK pin. This is a push-pull output. |
| SR | 4 | — | I | Slew rate adjust. This pin sets the slew rate of the H-bridge outputs. |
| SRC | 16 | 16 | O | Power FET source. Tie this pin to GND through a low-impedance path. |
| SRC | 17 | 17 | O | Power FET source. Tie this pin to GND through a low-impedance path. |
| VCP | 21 | 21 | PWR | Charge pump output. Connect a 16-V, 1-μF ceramic capacitor from this pin to the VM supply. |
| VM | 13 | 13 | PWR | Power supply. This pin is the motor supply voltage. Bypass this pin to GND with a 0.1-μF ceramic capacitor and a bulk capacitor. |
| VM | 20 | 20 | PWR | Power supply. This pin is the motor supply voltage. Bypass this pin to GND with a 0.1-μF ceramic capacitor and a bulk capacitor. |
| nFAULT | 2 | 2 | OD | Fault indication pin. This pin is pulled logic low with a fault condition. This open-drain output requires an external pullup resistor. |
| nSCS | — | 6 | I | Serial chip select. An active low on this pin enables the serial interface communications. Internal pullup to nSLEEP. |
| nSLEEP | 11 | 11 | I | Sleep input. To enter a low-power sleep mode, set this pin logic low. |