ZHCSQT3K October 2009 – January 2022 DRV8824
PRODUCTION DATA
請參考 PDF 數據表獲取器件具體的封裝圖。
Figure 5-1 PWP Package28-Pin HTSSOPTop View
Figure 5-2 RHD Package28-Pin VQFNTop View| PIN | I/O(1) | DESCRIPTION | EXTERNAL COMPONENTS OR CONNECTIONS | ||
|---|---|---|---|---|---|
| NAME | PWP | RHD | |||
| POWER AND GROUND | |||||
| GND | 14, 28 | 3, 17 | — | Device ground | |
| VMA | 4 | 7 | — | Bridge A power supply | Connect to motor supply (8.2 to 45 V). Both pins must be connected to same supply, bypassed with a 0.1-μF capacitor to GND, and connected to appropriate bulk capacitance. |
| VMB | 11 | 14 | — | Bridge B power supply | |
| V3P3OUT | 15 | 18 | O | 3.3-V regulator output | Bypass to GND with a 0.47-μF 6.3-V ceramic capacitor. Can be used to supply VREF. |
| CP1 | 1 | 4 | IO | Charge pump flying capacitor | Connect a 0.01-μF 50-V capacitor between CP1 and CP2. |
| CP2 | 2 | 5 | IO | Charge pump flying capacitor | |
| VCP | 3 | 6 | IO | High-side gate drive voltage | Connect a 0.1-μF 16-V ceramic capacitor. A 1-MΩ resistor can be connected to VM to accelerate discharge of the VCP capacitor. |
| CONTROL | |||||
| nENBL | 21 | 24 | I | Enable input | Logic high to disable device outputs and indexer operation, logic low to enable. Internal pulldown. |
| nSLEEP | 17 | 20 | I | Sleep mode input | Logic high to enable device, logic low to enter low-power sleep mode. Internal pulldown. |
| STEP | 22 | 25 | I | Step input | Rising edge causes the indexer to move one step. Internal pulldown. |
| DIR | 20 | 23 | I | Direction input | Level sets the direction of stepping. Internal pulldown. |
| MODE0 | 24 | 27 | I | Microstep mode 0 | MODE0 through MODE2 set the step mode: full, 1/2, 1/4, 1/8/ 1/16, or 1/32 step. Internal pulldown. |
| MODE1 | 25 | 28 | I | Microstep mode 1 | |
| MODE2 | 26 | 1 | I | Microstep mode 2 | |
| DECAY | 19 | 22 | I | Decay mode | Low = slow decay, Open =
mixed decay, High = fast decay. Internal pulldown and pullup. |
| nRESET | 16 | 19 | I | Reset input | Active-low reset input initializes the indexer logic and disables the H-bridge outputs. Internal pulldown. |
| AVREF | 12 | 15 | I | Bridge A current set reference input | Reference voltage for winding current set. Normally AVREF and BVREF are connected to the same voltage. Can be connected to V3P3OUT. |
| BVREF | 13 | 16 | I | Bridge B current set reference input | |
| NC | 23 | 26 | — | No connect | Leave this pin unconnected. |
| STATUS | |||||
| nHOME | 27 | 2 | OD | Home position | Logic low when at home state of step table |
| nFAULT | 18 | 21 | OD | Fault | Logic low when in fault condition (overtemperature, overcurrent) |
| OUTPUT | |||||
| ISENA | 6 | 9 | IO | Bridge A ground / Isense | Connect to current sense resistor for bridge A. |
| ISENB | 9 | 12 | IO | Bridge B ground / Isense | Connect to current sense resistor for bridge B. |
| AOUT1 | 5 | 8 | O | Bridge A output 1 | Connect to
bipolar stepper motor winding A. Positive current is AOUT1 → AOUT2 |
| AOUT2 | 7 | 10 | O | Bridge A output 2 | |
| BOUT1 | 10 | 13 | O | Bridge B output 1 | Connect to
bipolar stepper motor winding B. Positive current is BOUT1 → BOUT2 |
| BOUT2 | 8 | 11 | O | Bridge B output 2 | |