ZHCSQT3K October 2009 – January 2022 DRV8824
PRODUCTION DATA
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this analog current limit persists for longer than the OCP time, all FETs in the H-bridge will be disabled and the nFAULT pin will be driven low. The device remains disabled until either nRESET pin is applied, nSLEEP is toggled low and high, or VMx is removed and re-applied.
Overcurrent conditions on both high and low side devices, that is, a short to ground, supply, or across the motor winding, all result in an overcurrent shutdown. Note that overcurrent protection does not use the current sense circuitry used for PWM current control, and is independent of the ISENSE resistor value or xVREF voltage.