ZHCSP68C December 2021 – October 2022 DRV8328
PRODUCTION DATA
The gate driver device use a complimentary, push-pull topology for both the high-side and low-side drivers. This topology allows for both a strong pullup and pulldown of the external MOSFET gates. The low side gate drivers are supplied directly from the GVDD regulator supply. The operating mode of GVDD depends on the voltage of PVDD, when the PVDD >18V, the GVDD voltage is generated by an LDO, whereas PVDD < 18V, the GVDD voltage is generated by a charge pump. For the high-side gate drivers a bootstrap diode and capacitor are used to generate the floating high-side gate voltage supply. The bootstrap diode is integrated and an external bootstrap capacitor is used between BSTx and SHx pins. To support 100% duty cycle control, a trickle charge pump is integrated into the device. The trickle charge pump is connected to the BSTx node to prevent voltage drop due to the leakage currents of the driver and external MOSFET.
The high-side gate driver has a semi-active pulldown and low side gate has passive pulldown to help prevent the external MOSFET from turning ON during sleep state or when the power supply is disconnected.