ZHCSP68C December 2021 – October 2022 DRV8328
PRODUCTION DATA
If at any time the voltage on the GVDD pin falls lower than the VGVDD_UV threshold voltage for longer than the tGVDD_UV_DG time, the device detects a GVDD undervoltage event. After detecting the GVDD_UV undervoltage event, all of the gate driver outputs are driven low to disable the external MOSFETs, the charge pump is disabled and nFAULT pin is driven low. After the GVDD_UV condition is cleared, the fault state remains latched and can be cleared through an nSLEEP pin reset pulse (tRST)
After the GVDD_UV fault is cleared through an nSLEEP pin reset pulse, the nFAULT pin is held low until the GVDD capacitor is refreshed by the charge pump. After the GVDD capacitor is charged, the nFAULT pin is automatically released. The duration that the nFAULT pin is low after the fault is cleared will not exceed tWAKE time.