ZHCSP68C December 2021 – October 2022 DRV8328
PRODUCTION DATA
The device has adjustable VDS voltage monitors to detect overcurrent or short-circuit conditions on the external power MOSFETs. A MOSFET overcurrent event is sensed by monitoring the VDS voltage drop across the external MOSFET RDS(on). The high-side VDS monitors measure between the PVDD and SHx pins and the low-side VDS monitors measure between the SHx and LSS pins. If the voltage across external MOSFET exceeds the VDS_LVL threshold for longer than the tDS_DG deglitch time, a VDS_OCP event is recognized. Afer detecting the VDS overcurrent event, all of the gate driver outputs are driven low to disable the external MOSFETs and nFAULT pin is driven low. The VDS threshold can be set between 0.1 V to 2.5 V by applying a voltage on the VDSLVL pin. VDS OCP can be disabled by connecting VDSLVL to GVDD through a 100 kΩ resistor. After the VDS_OCP condition is cleared, the fault state remains latched and can be cleared through the nSLEEP pin reset pulse (tRST).