ZHCSP68C December 2021 – October 2022 DRV8328
PRODUCTION DATA
The nSLEEP pin manages the state of the DRV8328. When the nSLEEP pin is low, the device goes to a low-power sleep mode. In sleep mode, all gate drivers are disabled, all external MOSFETs are disabled, the GVDD regulator is disabled and the AVDD regulator is disabled. The tSLEEP time must elapse after a falling edge on the nSLEEP pin before the device goes to sleep mode. The device comes out of sleep mode automatically if the nSLEEP pin is pulled high. The tWAKE time must elapse before the device is ready for inputs.
During power up and power down of the device through the nSLEEP pin, the nFAULT pin is held low as the internal regulators are not active. After the regulators have been active, the nFAULT pin is automatically released. The duration that the nFAULT pin is low does not exceed the tSLEEP or tWAKE time.