ZHCSHZ0A April 2018 – July 2018 DRV8306
PRODUCTION DATA.
| PIN | TYPE(1) | DESCRIPTION | ||
|---|---|---|---|---|
| NAME | NO. | |||
| AGND | 25 | PWR | Device analog ground. Connect to system ground. | |
| CPH | 1 | PWR | Charge-pump switching node. Connect a X5R or X7R, 22-nF, VM-rated ceramic capacitor between the CPH and CPL pins. | |
| CPL | 32 | PWR | Charge-pump switching node. Connect a X5R or X7R, 22-nF, VM-rated ceramic capacitor between the CPH and CPL pins. | |
| DIR | 29 | I | Direction pin for setting the direction of the motor rotation to clockwise or counterclockwise. Internal pulldown resistor. | |
| DVDD | 26 | PWR | 3.3-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and AGND pins. This regulator can source up to 30 mA externally. | |
| ENABLE | 24 | I | Gate driver enable. When this pin is logic low the device enters a low-power sleep mode. A 15 to 40-µs low pulse can be used to reset fault conditions. | |
| FGOUT | 28 | OD | Outputs a commutation zero crossing signal generated from Hall sensors. | |
| GHA | 5 | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET. | |
| GHB | 11 | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET. | |
| GHC | 12 | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET. | |
| GLA | 7 | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET. | |
| GLB | 9 | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET. | |
| GLC | 14 | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET. | |
| HNA | 20 | I | Hall element negative input. Noise filter capacitors may be desirable, connected between the positive and negative Hall inputs. | |
| HNB | 18 | I | Hall element negative input. Noise filter capacitors may be desirable, connected between the positive and negative Hall inputs. | |
| HNC | 16 | I | Hall element negative input. Noise filter capacitors may be desirable, connected between the positive and negative Hall inputs. | |
| HPA | 19 | I | Hall element positive input. Noise filter capacitors may be desirable, connected between the positive and negative Hall inputs. | |
| HPB | 17 | I | Hall element positive input. Noise filter capacitors may be desirable, connected between the positive and negative Hall inputs. | |
| HPC | 15 | I | Hall element positive input. Noise filter capacitors may be desirable, connected between the positive and negative Hall inputs. | |
| IDRIVE | 22 | I | Gate drive output current setting. This pin is a 7 level input pin set by an external resistor. | |
| ISEN | 8 | I | Current sense for pulse-by-pulse current limit. Connect to low-side current sense resistor. | |
| PGND | 31 | PWR | Device power ground. Connect to system ground. | |
| PWM | 27 | I | PWM input for motor control. Set the output voltage and switching frequency of the phase voltage of the motor. | |
| SHA | 6 | I | High-side source sense input. Connect to the high-side power MOSFET source. | |
| SHB | 10 | I | High-side source sense input. Connect to the high-side power MOSFET source. | |
| SHC | 13 | I | High-side source sense input. Connect to the high-side power MOSFET source. | |
| VCP | 2 | PWR | Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VM pins. | |
| VDRAIN | 4 | I | High-side MOSFET drain sense input. Connect to the common point of the MOSFET drains. | |
| VDS | 23 | I | VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor. | |
| VM | 3 | PWR | Gate driver power supply input. Connect to the bridge power supply. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and PGND pins. | |
| nBRAKE | 30 | I | Causes motor to brake. Internal pulldown resistor. | |
| nFAULT | 21 | OD | Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor. | |