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ZHCSHZ0A April 2018 – July 2018 DRV8306

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

RSM|32
- MPQF195B

散熱焊盤機械數據 (封裝 | 引腳)

RSM|32
- QFND112H

訂購信息

6.5 Electrical Characteristics

at V_VM = 6 to 38 V over operating ambient temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER SUPPLIES (VM, DVDD)
I_VM	VM operating supply current	V_VM = 24 V; ENABLE = 1; PWM= 0 V		5	8	mA
I_VMQ	VM sleep mode supply current	ENABLE = 0; V_VM = 24 V, T_A = 25°C		20	40	µA
I_VMQ	VM sleep mode supply current	ENABLE = 0, V_VM = 24 V, T_A = 125°C			100	µA
t_RST	Reset pulse time	ENABLE = 0 V period to reset faults	15		40	µs
t_SLEEP	Sleep time	ENABLE = 0 V to driver tri-stated			200	µs
t_WAKE	Wake-up time	V_VM > V_UVLO; ENABLE = 3.3 V to output transistion			1	ms
V_DVDD	Internal logic regulator voltage	I_DVDD = 0 to 30 mA	2.9	3.3	3.6	V
CHARGE PUMP (VCP, CPH, CPL)
V_VCP	VCP operating voltage with respect to VM	V_M = 12 to 38 V; I_VCP = 0 to 15 mA	7	10	11.5	V
		V_M = 10 V; I_VCP = 0 to 10 mA	6.5	7.5	9.5
		V_M = 8 V; I_VCP = 0 to 5 mA	5	6	7.5
		V_M = 6 V; I_VCP = 0 to 1 mA	3.8	4.3	6.5
LOGIC-LEVEL INPUTS (PWM, DIR, nBRAKE)
V_IL	Input logic low voltage		0		0.8	V
V_IH	Input logic high voltage		1.5		5.5	V
V_HYS	Input logic hysteresis		100			mV
I_IL	Input logic low current	V_PIN (Pin Voltage) = 0 V	–1		1	µA
I_IH	Input logic high current	V_PIN (Pin Voltage) = 5 V			100	µA
R_PD	Pulldown resistance (PWM, DIR, nBRAKE)	Internal pulldown to AGND		100		kΩ
LOGIC-LEVEL INPUTS (ENABLE)
V_IL	Input logic low voltage		0		0.6	V
V_IH	Input logic high voltage		1.5		5.5	V
V_HYS	Input logic hysteresis		100			mV
I_IL	Input logic low current	V_PIN (Pin Voltage) = 0 V	–10		10	µA
I_IH	Input logic high current	V_PIN (Pin Voltage) = 5 V	–5		5	µA
SEVEN-LEVEL INPUTS (IDRIVE, VDS)
V_I1	Input mode 1 voltage	Tied to AGND		0		V
V_I2	Input mode 2 voltage	18 kΩ ± 5% to AGND		0.5		V
V_I3	Input mode 3 voltage	75 kΩ ± 5% to AGND		1.1		V
V_I4	Input mode 4 voltage	Hi-Z		1.65		V
V_I5	Input mode 5 voltage	75 kΩ ± 5% to DVDD		2.2		V
V_I6	Input mode 6 voltage	18 kΩ ± 5% to DVDD		2.8		V
V_I7	Input mode 7 voltage	Tied to DVDD		3.3		V
OPEN-DRAIN OUTPUTS (nFAULT, FGOUT)
V_OL	Output logic low voltage	I_OD = 2 mA			0.1	V
I_OZ	Output logic high current	V_OD = 5 V	–1		1	µA
GATE DRIVERS (GHX, SHX, GLX)
V_GHS	High-side V_GS gate drive (gate-to-source)	V_VM = 12 to 38 V; I_{HS_GATE} = 0 to 15 mA	7	10	11.5	V
		V_VM = 10 V; I_{HS_GATE} = 0 to 10 mA	6.5	7.5	8.5
		V_VM = 8 V; I_{HS_GATE} = 0 to 5 mA	5	6	7
		V_VM = 6 V; I_{HS_GATE} = 0 to 1 mA	3.8	4.3	6.5
V_GSL	Low-side V_GS gate drive (gate-to-source)	V_VM = 12 to 38 V; I_{LS_GATE} = 0 to 15 mA	7.5	10	12.5	V
		V_VM = 10 V; I_{LS_GATE} = 0 to 10 mA	5.5	7.5	9.5
		V_VM = 8 V; I_{LS_GATE} = 0 to 5 mA	3.5	6	8.5
		V_VM = 6 V; I_{LS_GATE} = 0 to 1 mA	3	4.3	6.5
t_DEAD	Output dead time			120		ns
t_DRIVE	Peak gate drive time			4000		ns
I_DRIVEP	Peak source gate current (high-side and low-side)	IDRIVE tied to AGND		15		mA
		IDRIVE 18 kΩ (±5%) to AGND		45
		IDRIVE 75 kΩ (±5%) to AGND		60
		IDRIVE Hi-Z ( > 500 kΩ to AGND)		90
		IDRIVE 75 kΩ (±5%) to DVDD		105
		IDRIVE 18 kΩ (±5%) to DVDD		135
		IDRIVE tied to DVDD		150
I_DRIVEN	Peak sink gate current (high-side and low-side)	IDRIVE tied to AGND		30		mA
		IDRIVE 18 kΩ (±5%) to AGND		90
		IDRIVE 75 kΩ (±5%) to AGND		120
		IDRIVE Hi-Z ( > 500 kΩ to AGND)		180
		IDRIVE 75 kΩ (±5%) to DVDD		210
		IDRIVE 18 kΩ (±5%) to DVDD		270
		IDRIVE tied to DVDD		300
I_HOLD	FET holding current	Source current after t_DRIVE		15		mA
I_HOLD	FET holding current	Sink current after t_DRIVE		30		mA
I_STRONG	FET hold-off strong pulldown	GHX and GLX		300		mA
R_OFF	FET gate hold-off resistor	GHX to SHXand GLX to PGND		150		kΩ
t_PD	Propagation delay	PWM transition to GHX/GLX transition		180	250	ns
HALL SENSOR INPUTS (HPX, HNX)
V_HYS	Hall comparator hysteresis voltage		20	30	40	mV
ΔV_HYS	Hall comparator hysteresis difference	Between A, B and C	-5		5	mV
V_ID	Hall comparator input differential		50			mV
V_CM	Hall comparator input common mode voltage CM range		1.5		3.5	V
I_I	Input leakage current	HPX = HNX = 0 V	–1		1	µA
t_HDEG	Hall deglitch time			5		µs
CYCLE-BY-CYCLE CURRENT LIMIT (ISEN)
V_LIMIT	Voltage limit across R_SENSEfor the current limiter		0.225	0.25	0.275	V
t_BLANK	Time that V_LIMIT is ignored from the start of the PWM cycle			5		µs
PROTECTION CIRCUITS
V_UVLO	VM undervoltage lockout	VM falling, UVLO report	5.4		5.8	V
V_UVLO	VM undervoltage lockout	VM rising, UVLO recovery	5.6		6	V
V_{UVLO_HYS}	VM undervoltage hysteresis	Rising to falling threshold		200		mV
t_{UVLO_DEG}	VM undervoltage deglitch time	VM falling, UVLO report		10		µs
V_CPUV	Charge pump undervoltage	With respect to VM		2.4		V
V_{GS_CLAMP}	Gate drive clamping voltage	Positive clamping voltage	10.5		15	V
V_{GS_CLAMP}	Gate drive clamping voltage	Negative clamping voltage		–0.6		V
V_{DS_OCP}	V_DS overcurrent trip voltage	VDS tied to AGND		0.15		V
		VDS 18 kΩ (±5%) to AGND		0.24
		VDS 75 kΩ (±5%) to AGND		0.4
		VDS Hi-Z ( > 500 kΩ to AGND)		0.6
		VDS 75 kΩ (±5%) to DVDD		0.9
		VDS 18 kΩ (±5%) to DVDD		1.8
		VDS tied to DVDD		Disabled
V_{SEN_OCP}	V_SENSE overcurrent trip voltage		1.7	1.8	1.9	V
t_{OCP_DEG}	V_DS and V_SENSE overcurrent deglitch time			4.5		µs
t_RETRY	Overcurrent retry time			4		ms
T_OTSD	Thermal shutdown temperature	Die temperature T_j	150	170		°C
T_HYS	Thermal hysteresis	Die temperature T_j		20		°C