ZHCSHZ0A April 2018 – July 2018 DRV8306
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Three Phase Smart Gate Drivers
- 7.3.2 DVDD Linear Voltage Regulator
- 7.3.3 Pulse-by-Pulse Current Limit
- 7.3.4 Hall Comparators
- 7.3.5 FGOUT Signal
- 7.3.6 Pin Diagrams
- 7.3.7 Gate-Driver Protective Circuits
- 7.4 Device Functional Modes
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
7.3.6 Pin Diagrams
Figure 22 shows the input structure for the logic-level pins, PWM, DIR and nBRAKE. The input can be driven with a voltage or external resistor.
Figure 22. Logic-Level Input Pin Structure (PWM, DIR, and nBRAKE) Figure 23 shows the input structure for the logic-level pin, ENABLE pin. The input can be driven with a voltage or external resistor. The VEXT represents the external voltage.
Figure 23. Logic-Level Input Pin Structure (ENABLE) Figure 24 shows the structure of the open-drain output pin, nFAULT. The open-drain output requires an external pullup resistor to function properly.
Figure 24. Open-Drain Output Pin Structure Figure 25 shows the structure of the seven level input pins, IDRIVE and VDS. The input can be set with an external resistor.
Figure 25. Seven Level Input Pin Structure