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ZHCSH31B August 2017 – February 2018 DRV10987

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

PWP|24
- MPDS372A

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

PWP|24
- PPTD264C

訂購(gòu)信息

7.5 Electrical Characteristics

over operating voltage and ambient temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY CURRENT (DRV10987D)
I_ccSLEEP1	Sleep current	V_SPEED = 0 V; V_CC= 12 V; T_A = 25℃		48	54	µA
I_ccSLEEP1	Sleep current	V_SPEED = 0 V; V_CC = 12 V; across temperature			81	µA
I_cc	Active current	V_SPEED> 0 V; step-down regulator with inductor (buck mode); no motor load		10	15	mA
I_cc	Active current	V_SPEED> 0 V; step-down regulator with resistor (linear mode); no motor load		13	16	mA
SUPPLY CURRENT (DRV10987S)
I_ccSTBY	Standby current	V_SPEED = 0 V; step-down regulator with inductor (buck mode)		8.5	14	mA
I_ccSTBY	Standby current	V_SPEED = 0 V; buck regulator with resistor (linear mode)		11	15	mA
I_cc	Active current	V_SPEED> 0 V; buck regulator with inductor; no motor load		10	15	mA
I_cc	Active current	V_SPEED> 0 V; buck regulator with resistor; no motor load		13	16	mA
UVLO
V_{UVLO_R}	UVLO rising threshold voltage		5.8	6	6.2	V
V_{UVLO_F}	UVLO falling threshold voltage		5.6	5.8	6	V
V_{UVLO_HYS}	UVLO threshold voltage hysteresis		170	195	220	mV
V_{V1P8_UVLO_R}	V1P8 UVLO rising threshold		1.5	1.6	1.7	V
V_{V1P8_UVLO_F}	V1P8 UVLO falling threshold		1.4	1.55	1.65	V
V_{V3P3_UVLO_R}	V3P3 UVLO rising threshold		2.7	2.85	2.95	V
V_{V3P3_UVLO_F}	V3P3 UVLO falling threshold		2.5	2.7	2.8	V
V_{VREG_UVLO_R}	VREG UVLO rising threshold		4	4.2	4.3	V
V_{VREG_UVLO_F}	VREG UVLO falling threshold		3.9		4.2	V
LDO OUTPUT
V3P3	Output voltage	Step-down regulator with inductor (buck mode), 20-mA load	3.1	3.3	3.5	V
V3P3	Output voltage	Step-down regulator with resistor (linear mode), no load	3.1	3.3	3.5	V
I_{V3P3_MAX}	Maximum load from V3P3	Step-down regulator with inductor (buck mode)			20	mA
V1P8	Output voltage	No load	1.7	1.8	1.9	V
STEP-DOWN REGULATOR
V_REG	Regulator output voltage	L_SW = 47 µH, C_SW = 10 µF I_load = 100 mA	4.5	5	5.5	V
V_REG	Regulator output voltage	R_SW = 39 Ω, C_SW = 10 µF I_load = 5 mA	4.5	5	5.5	V
I_{REG_MAX_L}	Maximum load from V_REG in buck mode	L_SW = 47 µH, C_SW = 10 µF			100	mA
I_{REG_MAX_R}	Maximum load from V_REG in linear mode	R_SW = 39 Ω, C_SW = 10 µF			5	mA
INTEGRATED MOSFET
r_DS(ON)	Series resistance (H + L)	T_A = 25?C; V_CC> 6.5 V; I_O = 1 A		250	400	mΩ
r_DS(ON)	Series resistance (H + L)	T_A = 125?C; V_CC> 6.5V; I_O = 1 A		325	550	mΩ
SPEED – ANALOG MODE
V_{AN/A_FS}	Analog full-speed voltage		V_(V3P3) × 0.9		V_(V3P3)	V
V_{AN/A_ZS}	Analog zero-speed voltage		0		100	mV
t_SAM	Sampling period for analog voltage on SPEED pin			320		µs
V_{AN/A_RES}	Analog voltage resolution			6.5		mV
SPEED – PWM DIGITAL MODE
V_{DIG_IH}	PWM input high voltage		2.2			V
V_{DIG_IL}	PWM input low voltage				0.6	V
ƒ_PWM	PWM input frequency		0.1		100	kHz
SLEEP MODE (DRV10987D)
V_{EN_SL}	Analog voltage to enter sleep mode	SpdCtrlMd = 0 (analog mode)			100	mV
V_{EX_SL}	Analog voltage to exit sleep mode	SpdCtrlMd = 0 (analog mode)	2.2			V
t_{EX_SL_ANA}	Time needed to exit from sleep mode	SpdCtrlMd = 0 (analog mode) V_SPEED> V_{EX_SL}		2		µs
t_{EX_SL_DR_ANA}	Time taken to drive motor after exiting from sleep mode	SpdCtrlMd = 0 (analog mode) V_SPEED> V_{EN_SL}; ISDen = 0; BrkDoneThr[2:0] = 0		350		ms
t_{EX_SL_PWM}	Time needed to exit from sleep mode	SpdCtrlMd = 1 (PWM mode) V_SPEED> V_{DIG_IH}		2		µs
t_{EX_SL_DR_PWM}	Time taken to drive motor after exiting from sleep mode	SpdCtrlMd = 1 (PWM mode) V_SPEED> V_{DIG_IH}; ISDen = 0; BrkDoneThr[2:0] = 0		350		ms
t_{EN_SL_ANA}	Time needed to enter sleep mode	SpdCtrlMd = 0 (analog mode) V_SPEED< V_{EN_SL}; AvSIndEn = 0		6		ms
t_{EN_SL_PWM}	Time needed to enter sleep mode	SpdCtrlMd = 1 (PMW mode) V_SPEED< V_{DIG_IL}; AvSIndEn = 0		60		ms
R_{PD_SPEED_SL}	Internal SPEED pin pull down resistance to ground	V_SPEED = 0 (Sleep mode)	55			kΩ
STANDBY MODE (DRV10987S)
V_{EN_SB}	Analog voltage to enter standby mode	SpdCtrlMd = 0 (analog mode)			100	mV
V_{EX_SB}	Analog voltage to exit standby mode	SpdCtrlMd = 0 (analog mode)	0.17			V
t_{EX_SB_ANA}	Time needed to exit from standby mode	SpdCtrlMd = 0 (analog mode) V_SPEED> V_{EX_SB}	1		700	ms
t_{EX_SB_DR_ANA}	Time taken to drive motor after exiting standby mode	SpdCtrlMd = 0 (analog mode) V_SPEED> V_{EN_SB}; ISDen = 0; BrkDoneThr[2:0] = 0		350		ms
t_{EX_SB_PWM}	Time needed to exit from standby mode	SpdCtrlMd = 1 (PWM mode) V_SPEED> V_{DIG_IH}		2		µs
t_{EX_SB_DR_PWM}	Time taken to drive motor after exiting standby mode	SpdCtrlMd = 1 (PWM mode) V_{SPEED_DUTY}> 0; ISDen = 0; BrkDoneThr[2:0] = 0		350		ms
t_{EN_SB_ANA}	Time needed to enter standby mode	SpdCtrlMd = 0 (analog mode) V_SPEED< V_{EN_SB}; AvSIndEn = 0		6		ms
t_{EN_SB_PWM}	Time needed to enter standby mode	SpdCtrlMd = 1 (PMW mode) V_SPEED< V_{DIG_IL;} AvSIndEn = 0		60		ms
DIGITAL I/O (DIR INPUT, FG OUTPUT)
V_{DIR_H}	Input high		2.2			V
V_{DIR_L}	Input low				0.6	V
V_{FG_OH}	Output high voltage	I_o = 5 mA		3.3		V
V_{FG_OL}	Output low voltage	I_o= 5 mA			0.6	V
I²C SERIAL INTERFACE
V_{I2C_H}	Input high		2.2			V
V_{I2C_L}	Input low				0.6	V
f_I2C	I²C clock frequency		0		400	kHz
LOCK DETECTION RELEASE TIME
t_{LOCK_OFF}	Lock release time			5		s
t_{LCK_ETR}	Lock enter time			0.3		s
OVERCURRENT PROTECTION
I_{OC_limit_HS}	HS overcurrent protection	V_CC< 28.5 V	3.5	4.25	5.5	A
I_{OC_limit_LS}	LS overcurrent protection	V_CC< 28.5 V	3.5	4.25	5.5	A
THERMAL SHUTDOWN
T_SDN	Junction temperature shutdown threshold		150	165	180	°C
T_{SDN_HYS}	Junction temperature shutdown hysteresis		15	20	25	°C
T_WARN	Junction temperature warning threshold		115	125	140	°C
PHASE DRIVER
SL_{PH_LH0}	Phase slew rate switching low to high	PHslew = 0; measure 20% to 80%; V_CC = 12 V	85	120	145	V/µs
SL_{PH_LH1}	Phase slew rate switching low to high	PHslew = 1; measure 20% to 80%; V_CC = 12 V	60	80	100	V/µs
SL_{PH_LH2}	Phase slew rate switching low to high	PHslew = 2; measure 20% to 80%; V_CC= 12 V	38	50	62	V/µs
SL_{PH_LH3}	Phase slew rate switching low to high	PHslew = 3; measure 20% to 80%; V_CC = 12 V	27	35	44	V/µs
SL_{PH_HL0}	Phase slew rate switching high to low	PHslew = 0; measure 80% to 20%; V_CC = 12 V	85	120	145	V/µs
SL_{PH_HL1}	Phase slew rate switching high to low	PHslew = 1; measure 80% to 20%; V_CC = 12 V	59	80	100	V/µs
SL_{PH_HL2}	Phase slew rate switching high to low	PHslew = 2; measure 80% to 20%; V_CC = 12 V	36	50	60	V/µs
SL_{PH_HL3}	Phase slew rate switching high to low	PHslew = 3; measure 80% to 20%; V_CC = 12 V	25	35	45	V/µs
EEPROM
EE_Prog	Programing voltage		6.2			V
EE_RET	Retention		10			Years
EE_END	Endurance		1000			Cycles
OVERVOLTAGE PROTECTION
V_{OV_R}	Overvoltage protection rising V_CC threshold		28.5	29.2	30	V
V_{OV_F}	Overvoltage protection exit on falling V_CC threshold		27.7	28.2	28.8	V
V_{OV_HYS}	Overvoltage protection hysteresis		0.73	1	1.1	V
BEMF COMPARATOR
BEMF_HYS	BEMF comparator hysteresis	BEMF_HYS = 0	7	20	30	mV
BEMF_HYS	BEMF comparator hysteresis	BEMF_HYS = 1	17	40	51	mV

Figure 1. DRV10987D Analog Mode Timing

Figure 2. DRV10987D PWM Mode Timing

Figure 3. DRV10987S Analog Mode Timing

Figure 4. DRV10987S PWM Mode Timing