ZHCSQQ1B june 2022 – august 2023 ADC32RF54 , ADC32RF55
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics - Power Consumption
- 6.6 Electrical Characteristics - DC Specifications
- 6.7 Electrical Characteristics - ADC32RF54 AC Specifications (Dither DISABLED)
- 6.8 Electrical Characteristics - ADC32RF54 AC Specifications (Dither ENABLED)
- 6.9 Electrical Characteristics - ADC32RF55 AC Specifications (Dither DISABLED)
- 6.10 Electrical Characteristics - ADC32RF55 AC Specifications (Dither ENABLED)
- 6.11 Timing Requirements
- 6.12 Typical Characteristics - ADC32RF54
- 6.13 Typical Characteristics - ADC32RF55
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Analog Inputs
- 7.3.2 Sampling Clock Input
- 7.3.3 SYSREF
- 7.3.4 ADC Foreground Calibration
- 7.3.5 Decimation Filter
- 7.3.6
JESD204B Interface
- 7.3.6.1 JESD204B Initial Lane Alignment (ILA)
- 7.3.6.2 JESD204B Frame Assembly
- 7.3.6.3 JESD204B Frame Assembly in Bypass Mode
- 7.3.6.4 JESD204B Frame Assembly with Complex Decimation - Single Band
- 7.3.6.5 JESD204B Frame Assembly with Real Decimation - Single Band
- 7.3.6.6 JESD204B Frame Assembly with Complex Decimation - Dual Band
- 7.3.6.7 JESD204B Frame Assembly with Complex Decimation - Quad Band
- 7.3.7 SERDES Output MUX
- 7.3.8 Test Pattern
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6 Register Maps
-
8 Application and Implementation
- 8.1 Application Information
- 8.2 Typical Applications
- 8.3
Initialization Set Up
- 8.3.1
Initial Device Configuration After Power-Up
- 8.3.1.1 STEP 1: RESET
- 8.3.1.2 STEP 2: Device Configuration
- 8.3.1.3 STEP 3: JESD Interface Configuration (1)
- 8.3.1.4 STEP 4: SYSREF Synchronization
- 8.3.1.5 STEP 5: JESD Interface Configuration (2)
- 8.3.1.6 STEP 6: Analog Trim Settings
- 8.3.1.7 STEP 7: Calibration Configuration
- 8.3.1.8 STEP 8: SYSREF Synchronization
- 8.3.1.9 STEP 9: Run Power up Calibration
- 8.3.1.10 STEP 10: JESD Interface Synchronization
- 8.3.1
Initial Device Configuration After Power-Up
- 8.4 Power Supply Recommendations
- 8.5 Layout
- 9 Device and Documentation Support
- 10Mechanical, Packaging, and Orderable Information
7.3.7 SERDES Output MUX
The SERDES output block contains one digital mux per SERDES output lane with a 3-bit register. This allows routing any of the 8 digital streams to any output serdes transmitter as shown in the example in Figure 7-43. The MUX can be used to reorder lanes as well as duplicate lane outputs (for example in LMFS = 1-4-8-1 mode the same output stream could be duplicated on all 8 lanes).
Figure 7-43 SERDES output mux for DOUT0By default after power, the active SERDES lanes start on lane DOUT0 as shown for the complex decimation dual band example in Table 7-45. After power up, the output is transmitted on lanes DOUT0..3. Using the digital output muxes, the output data for channel B is shifted from lanes DOUT2,3 to DOUT4,5. All SERDES transmitters are powered up and enabled by default. After configuring the output mux unused lanes can be powered down to save power consumption.
| OUTPUT LANE | Default | Using MUX | ||||||
|---|---|---|---|---|---|---|---|---|
| DOUT0 | A1I0 [15:8] | A1I0 [7:0] | A1Q0 [15:8] | A1Q0 [7:0] | A1I0 [15:8] | A1I0 [7:0] | A1Q0 [15:8] | A1Q0 [7:0] |
| DOUT1 | A2I0 [15:8] | A2I0 [7:0] | A2Q0 [15:8] | A2Q0 [7:0] | A2I0 [15:8] | A2I0 [7:0] | A2Q0 [15:8] | A2Q0 [7:0] |
| DOUT2 | B1I0 [15:8] | B1I0 [7:0] | B1Q0 [15:8] | B1Q0 [7:0] | ||||
| DOUT3 | B2I0 [15:8] | B2I0 [7:0] | B2Q0 [15:8] | B2Q0 [7:0] | ||||
| DOUT4 | B1I0 [15:8] | B1I0 [7:0] | B1Q0 [15:8] | B1Q0 [7:0] | ||||
| DOUT5 | B2I0 [15:8] | B2I0 [7:0] | B2Q0 [15:8] | B2Q0 [7:0] | ||||
| DOUT6 | ||||||||
| DOUT7 | ||||||||
Table 7-46 shows the register writes to shift the output lanes from default as illustrated in Table 7-45.
| ADDR | DATA | DESCRIPTION |
|---|---|---|
| 0x05 | 0x04 | Select JESD page |
| 0x81 | 0x54 | Select internal JESD streams 4 and 5 to lanes DOUT2 and DOUT3 |
| 0x82 | 0x32 | Select internal JESD streams 2 and 3 to lanes DOUT4 and DOUT5 |