ZHCSQQ1B june 2022 – august 2023 ADC32RF54 , ADC32RF55
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics - Power Consumption
- 6.6 Electrical Characteristics - DC Specifications
- 6.7 Electrical Characteristics - ADC32RF54 AC Specifications (Dither DISABLED)
- 6.8 Electrical Characteristics - ADC32RF54 AC Specifications (Dither ENABLED)
- 6.9 Electrical Characteristics - ADC32RF55 AC Specifications (Dither DISABLED)
- 6.10 Electrical Characteristics - ADC32RF55 AC Specifications (Dither ENABLED)
- 6.11 Timing Requirements
- 6.12 Typical Characteristics - ADC32RF54
- 6.13 Typical Characteristics - ADC32RF55
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Analog Inputs
- 7.3.2 Sampling Clock Input
- 7.3.3 SYSREF
- 7.3.4 ADC Foreground Calibration
- 7.3.5 Decimation Filter
- 7.3.6
JESD204B Interface
- 7.3.6.1 JESD204B Initial Lane Alignment (ILA)
- 7.3.6.2 JESD204B Frame Assembly
- 7.3.6.3 JESD204B Frame Assembly in Bypass Mode
- 7.3.6.4 JESD204B Frame Assembly with Complex Decimation - Single Band
- 7.3.6.5 JESD204B Frame Assembly with Real Decimation - Single Band
- 7.3.6.6 JESD204B Frame Assembly with Complex Decimation - Dual Band
- 7.3.6.7 JESD204B Frame Assembly with Complex Decimation - Quad Band
- 7.3.7 SERDES Output MUX
- 7.3.8 Test Pattern
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6 Register Maps
-
8 Application and Implementation
- 8.1 Application Information
- 8.2 Typical Applications
- 8.3
Initialization Set Up
- 8.3.1
Initial Device Configuration After Power-Up
- 8.3.1.1 STEP 1: RESET
- 8.3.1.2 STEP 2: Device Configuration
- 8.3.1.3 STEP 3: JESD Interface Configuration (1)
- 8.3.1.4 STEP 4: SYSREF Synchronization
- 8.3.1.5 STEP 5: JESD Interface Configuration (2)
- 8.3.1.6 STEP 6: Analog Trim Settings
- 8.3.1.7 STEP 7: Calibration Configuration
- 8.3.1.8 STEP 8: SYSREF Synchronization
- 8.3.1.9 STEP 9: Run Power up Calibration
- 8.3.1.10 STEP 10: JESD Interface Synchronization
- 8.3.1
Initial Device Configuration After Power-Up
- 8.4 Power Supply Recommendations
- 8.5 Layout
- 9 Device and Documentation Support
- 10Mechanical, Packaging, and Orderable Information
7.3.1.1 Input Bandwidth and Full-Scale
The input bandwidth (-3 dB) and input fullscale are dependent on what input termination and averaging mode are chosen as shown in the summary in Table 7-50. With 4x averaging enabled, the -3 dB bandwidth reduces to ~ 2.1 GHz and 100 Ω differential termination - the bandwidth can be increased by changing the input termination to 50 Ω differential.
Table 7-1 Digital averaging vs Full Power Input Bandwidth (–3 dB)
| # of ADCs averaged | ADC inputs used for averaging | Input Bandwidth (-3 dB) | Selected differential input termination | Effective differential input termination | Input Full-scale |
|---|---|---|---|---|---|
| Default | INx1 | 2.75 GHz | 100 Ω | 100 Ω | + 2 dBm |
| 2 | INx1 | 2.75 GHz | 100 Ω | 100 Ω | + 3.5 dBm |
| 4 | INx1, INx2 | 2.1 GHz | 100 Ω | 50 Ω | + 6.6 dBm |
The full power input bandwidth plots with input RESET switch disabled (RSW0) and enabled (RSW1) are shown in Figure 7-2.
Figure 7-2 Input Bandwidth - Reset switch
DISThe RESET switch is enabled by default and can be disabled with the following register writes:
Table 7-2 Register Write Example for Configuring
the RESET Switch
| ADDR | DATA | DESCRIPTION |
|---|---|---|
| 0x05 | 0x40 | Select ANALOG page |
| 0x6D | 0xC0 | Disable RESET Switch (to enable: 0x00) |
| 0x6E | 0x08 | Disable RESET Switch (to enable: 0x00) |