ZHCSQQ1B june 2022 – august 2023 ADC32RF54 , ADC32RF55
PRODUCTION DATA
The ADC32RF5x is a single core (non-interleaved) 14-bit, 2.6 GSPS to 3 GSPS, dual channel analog to digital converter (ADC). The design maximizes signal-to-noise ratio (SNR) and delivers a noise spectral density of -155 dBFS/Hz. Additional internal ADCs can be used for on-chip averaging (2x and 4x) to further improve the noise density to as low as -161 dBFS/Hz.
The analog signal input is non-buffered to save power consumption with a nominal differential input impedance of 100 Ω. The full power input bandwidth is 2.75 GHz (-3 dB) and the device supports direct RF sampling with input frequencies in the through the L-band. The device is designed for low residual phase noise to support high performance radar applications. The sampling clock input has a dedicated power supply input which requires a very clean power supply.
Each ADC channel can be connected to a quad-band digital down-converter (DDC) using a 48-bit NCO which supports phase coherent frequency hopping. Using the GPIO pins for NCO frequency control, frequency hopping can be achieved in less than 1 μs. The digital down converters support a wide range of instantaneous bandwidth (IBW) coverage - from single wide band mode with 4x complex decimation to up to four narrow bandwidth channels with as high as 128x complex decimation.
The ADC32RF5x supports the JESD204B serial data interface with subclass 1 deterministic latency using data rates up to 13.0 Gbps. In bypass mode, 14-bit output is supported up to a sampling rate of 2.6 Gsps. From 2.6 to 3 Gsps a 12-bit interface with more efficient data packing can be used at expense of quantization noise. When using decimation the output is 16-bit.