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ZHCSGI8A April 2017 – October 2021 ADC12D1620QML-SP

PRODUCTION DATA

封裝選項

請參考 PDF 數據表獲取器件具體的封裝圖。

機械數據 (封裝 | 引腳)

FVA|256
NAA|376

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

zhcsgi8a_oa

6.11 Converter Electrical Characteristics: Digital Control and Output Pin Characteristics

The following specifications apply after calibration for for V_A = V_DR = V_TC = V_E = 1.9 V; I and Q channels AC-coupled, FSR pin = High; C_L = 10 pF; differential AC-coupled sine wave input clock, f_CLK = 1.6 GHz at 0.5 V_P-P with 50% duty cycle; V_BG = floating; non-extended control mode; Rext = Rtrim = 3300 ? ±0.1%; analog signal source impedance = 100-Ω differential; 1:2 demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on.⁽¹⁾⁽²⁾

PARAMETER		CONDITIONS	SUB-GROUPS	MIN	TYP⁽³⁾	MAX	UNIT
DIGITAL CONTROL PINS, (DES, LSPSM, CAL, PDI, PDQ, TPM, NDM, FSR, DDRPh, ECE, SCLK, SDI, SCS— unless otherwise specified)
V_IH	Logic high input voltage		[1, 2, 3]	0.7 x V_A			V
V_IL	Logic low input voltage		[1, 2, 3]			0.3 x V_A	V
I_IH	Input leakage current	V_IN = V_A	[1, 2, 3]	–1		1	μA
I_IL	Input leakage current (DES, LSPSM, CAL, TPM, NDM, FSR, DDRPh)	V_IN = GND	[1, 2, 3]	–1		1	μA
	Input leakage current (SCLK, SDI, SCS)		[1, 2, 3]	–30			μA
	Input leakage current (PDI, PDQ, ECE)		[1, 2, 3]	–55			μA
C_{IN_DIG}	Input capacitance⁽⁴⁾	Each input to ground			1.5		pF
DIGITAL OUTPUT PINS (Data, DCLKI, DCLKQ, ORI, ORQ) - see Device Nomenclature
V_OD	LVDS differential output voltage	V_BG = floating, OVS = High	[1, 2, 3]	380	600	840	mV_P-P
		V_BG = floating, OVS = Low	[1, 2, 3]	240	440	650	mV_P-P
		V_BG = V_A, OVS = high	[1, 2, 3]		670		mV_P-P
		V_BG = V_A, OVS = low	[1, 2, 3]		500		mV_P-P
ΔV_{O DIFF}	Change in LVDS output swing between logic levels			-20	1	20	mV
V_OS	Output offset voltage	V_BG = floating			0.8		V
V_OS	Output offset voltage	V_BG = V_A			1.2		V
ΔV_OS	Change in output offset voltage between logic levels				±1		mV
I_OS	Output short-circuit current	V_BG = floating; D+ and D? connected to 0.8 V			±3.8		mA
Z_O	Differential output impedance				100		?
DIFFERENTIAL DCLK RESET PINS (DCLK_RST)
V_{CMI_DRST}	DCLK_RST Common mode Input Voltage				1.25		V
V_{ID_DRST}	Differential DCLK_RST Input Voltage				0.6		V_P-P
R_{IN_DRST}	Differential DCLK_RST Input Resistance⁽⁵⁾				100		?
DIGITAL OUTPUT PINS (CalRun, SDO)
V_OH	Logic high output level	CalRun, SDO I_OH = ?400 μA	[1, 2, 3]	1.5	1.7		V
V_OL	Logic low output level	CalRun, SDO I_OH = 400 μA	[1, 2, 3]		0.14	0.3	V

(1) The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.

(2) To ensure accuracy, it is required that V_A, V_TC, V_E and V_DR be well bypassed. Each supply pin must be decoupled with separate bypass capacitors.

(3) Typical figures are at T_A = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average outgoing quality level (AOQL).

(4) The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6-pF each pin to ground are isolated from the die capacitances by lead and bond wire inductances.

(5) This parameter is specified by design and/or characterization and is not tested in production.