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ZHCSGI8A April 2017 – October 2021 ADC12D1620QML-SP

PRODUCTION DATA

封裝選項(xiàng)

請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。

機(jī)械數(shù)據(jù) (封裝 | 引腳)

FVA|256
NAA|376

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購信息

zhcsgi8a_oa

6.7 Converter Electrical Characteristics: Analog Input/Output and Reference Characteristics

The following specifications apply after calibration for V_A = V_DR = V_TC = V_E = 1.9 V; I and Q channels AC-coupled, FSR pin = high; C_L = 10-pF; differential AC-coupled sine wave input clock, f_CLK = 1.6 GHz at 0.5 V_P-P with 50% duty cycle; V_BG = floating; non-extended control mode; Rext = Rtrim = 3300 ? ±0.1%; analog signal source impedance = 100-Ω differential; 1:2 demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on.⁽¹⁾⁽²⁾

PARAMETER		TEST CONDITIONS	SUB-GROUPS	MIN	TYP⁽³⁾	MAX	UNIT
V_{IN_FSR}	Analog differential input full-scale range	FSR pin Y3 Low	[4, 5, 6]		630		mV_P-P
		FSR pin Y3 High	[4, 5, 6]	750	820	890	mV_P-P
		EXTENDED CONTROL MODE
		FM(14:0) = 0000h			600		mV_P-P
		FM(14:0) = 4000h (default)			800		mV_P-P
		FM(14:0) = 7FFFh			1000		mV_P-P
C_IN	Analog input capacitance, Non-DES mode ⁽⁴⁾⁽⁵⁾	Differential			0.02		pF
	Analog input capacitance, Non-DES mode ⁽⁴⁾⁽⁵⁾	Each input pin to ground			1.6		pF
	Analog input capacitance, DES mode ⁽⁴⁾⁽⁵⁾	Differential			0.02		pF
	Analog input capacitance, DES mode ⁽⁴⁾⁽⁵⁾	Each input pin to ground			2.2		pF
R_IN	Differential input resistance		[1, 2, 3]	99	103	107	?
COMMON-MODE OUTPUT
V_CMO	Common-mode output voltage	I_CMO = ±100 μA	[1, 2, 3]	1.15	1.25	1.35	V
TC_V_CMO	Common-mode output voltage temperature coefficient	I_CMO = ±100 μA			38		ppm/°C
V_{CMO_LVL}	V_CMO input threshold to set DC-coupling mode				0.63		V
C_L_V_CMO	Maximum V_CMO load capacitance	See⁽⁵⁾				80	pF
BANDGAP REFERENCE
V_BG	Bandgap reference output voltage	I_BG = ±100 μA	[1, 2, 3]	1.15	1.27	1.35	V
TC_V_BG	Bandgap reference voltage temperature coefficient	I_BG = ±100 μA			50		ppm/°C
C_LOAD V_BG	Maximum bandgap reference load capacitance				80		pF

(1) The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.

(2) To ensure accuracy, it is required that V_A, V_TC, V_E and V_DR be well bypassed. Each supply pin must be decoupled with separate bypass capacitors.

(3) Typical figures are at T_A = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average outgoing quality level (AOQL).

(4) The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.22-pF differential and 1.06-pF each pin to ground are isolated from the die capacitances by lead and bond wire inductances.

(5) This parameter is specified by design and/or characterization and is not tested in production.