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ZHCSGI8A April 2017 – October 2021 ADC12D1620QML-SP

PRODUCTION DATA

封裝選項

請參考 PDF 數據表獲取器件具體的封裝圖。

機械數據 (封裝 | 引腳)

FVA|256
NAA|376

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

zhcsgi8a_oa

6.6 Converter Electrical Characteristics: Dynamic Converter Characteristics

The following specifications apply after calibration for V_A = V_DR = V_TC = V_E = 1.9 V; I and Q channels AC-coupled, FSR pin = high; C_L = 10 pF; differential AC-coupled sine wave input clock, f_CLK = 1.6 GHz at 0.5 V_P-P with 50% duty cycle; V_BG = floating; non-extended control mode; Rext = Rtrim = 3300 ? ±0.1%; analog signal source impedance = 100-Ω differential; 1:2 demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on.⁽¹⁾⁽²⁾

PARAMETER		TEST CONDITIONS	SUB-GROUPS	MIN	TYP⁽³⁾	MAX	UNIT
CER	Code error rate				10^–18		Error/ Sample
IMD₃	3rd order intermodulation distortion	f_IN = 2070 MHz ± 2.5 MHz at –13 dBFS			–76		dBFS
		f_IN = 2070 MHz ± 2.5 MHz at –13 dBFS			–63		dBc
		f_IN = 2070 MHz ± 2.5 MHz at –16 dBFS			–80		dBFS
		f_IN = 2070 MHz ± 2.5 MHz at –16 dBFS			–64		dBc
		f_IN = 2670 MHz ± 2.5 MHz at –13 dBFS			–72		dBFS
		f_IN = 2670 MHz ± 2.5 MHz at –13 dBFS			–59		dBc
		f_IN = 2670 MHz ± 2.5 MHz at –16 dBFS			–77		dBFS
		f_IN = 2670 MHz ± 2.5 MHz at –16 dBFS			–61		dBc
1:2 DEMUX, NON-DES MODE, NON-ECM, NON-LSPSM, f_CLK = 1.6 GHz, f_IN = 248 MHz, V_IN = –0.5 dBFS
ENOB	Effective number of bits		[4]	8.8	9.1		bits
			[5]	8.7
			[6]	8.4
SINAD	Signal-to-noise plus distortion ratio		[4]	54.7	56.5		dBFS
			[5]	54.1
			[6]	52.3
SNR	Signal-to-noise ratio		[4]	56	58.4		dBFS
			[5]	54.6			dBFS
			[6]	53.5			dBFS
THD	Total harmonic distortion		[4, 5]		–62	–59.2	dBFS
THD	Total harmonic distortion		[6]			–55.5	dBFS
2nd Harm	Second harmonic distortion				–72.2		dBFS
3rd Harm	Third harmonic distortion				–62.1		dBFS
SFDR	Spurious-free dynamic range		[4]	58.9	62.1		dBFS
			[5]	58.1			dBFS
			[6]	56			dBFS
1:2 DEMUX, NON-DES MODE, NON-ECM, LSPSM, f_CLK = 800 MHz, f_IN = 248 MHz, V_IN = –0.5 dBFS
ENOB	Effective number of bits		[4, 5]	9.1	9.5		bits
ENOB	Effective number of bits		[6]	8.6			bits
SINAD	Signal-to-noise plus distortion ratio		[4, 5]	56.5	58.6		dBFS
SINAD	Signal-to-noise plus distortion ratio		[6]	53.5			dBFS
SNR	Signal-to-noise ratio		[4, 5]	57.6	59.8		dBFS
SNR	Signal-to-noise ratio		[6]	56.8			dBFS
THD	Total harmonic distortion		[4, 5]		–67	–62.3	dBFS
THD	Total harmonic distortion		[6]			–57	dBFS
2nd Harm	Second harmonic distortion				–77.7		dBFS
3rd Harm	Third harmonic distortion				–67.5		dBFS
SFDR	Spurious-free dynamic range		[4, 5]	62.5	67.4		dBFS
SFDR	Spurious-free dynamic range		[6]	57.5			dBFS
NON-DEMUX, NON-DES MODE, ECM, NON-LSPSM, f_CLK = 1.6 GHz, f_IN = 248 MHz, V_IN = –0.5 dBFS
ENOB	Effective number of bits				9.1		bits
SINAD	Signal-to-noise plus distortion ratio				56.6		dBFS
SNR	Signal-to-noise ratio				58.6		dBFS
THD	Total harmonic distortion				–63.2		dBFS
2nd Harm	Second harmonic distortion				–72		dBFS
3rd Harm	Third harmonic distortion				–63.3		dBFS
SFDR	Spurious-free dynamic range				63.3		dBFS
1:4 DEMUX, DES MODE, NON-LSPSM, f_CLK = 1.6 GHz, f_IN = 248 MHz, V_IN = –0.5 dBFS
ENOB	Effective number of bits				8.9		bits
SINAD	Signal-to-noise plus distortion ratio				55.5		dB
SNR	Signal-to-noise ratio				56.9		dBFS
THD	Total harmonic distortion				–62.3		dBFS
2nd Harm	Second harmonic distortion				–79.1		dBFS
3rd Harm	Third harmonic distortion				–62.3		dBFS
SFDR	Spurious-free dynamic range				61.7		dBFS

(1) The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.

(2) To ensure accuracy, it is required that V_A, V_TC, V_E and V_DR be well bypassed. Each supply pin must be decoupled with separate bypass capacitors.

(3) Typical figures are at T_A = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average outgoing quality level (AOQL).