ZHCSGI8A April 2017 – October 2021 ADC12D1620QML-SP
PRODUCTION DATA
The ADC12D1620 offers many features to make the device convenient to use in a wide variety of applications. Table 7-1 is a summary of the features available, as well as details for the control mode chosen. N/A means Not Applicable.
| FEATURE | NON-ECM | CONTROL PIN ACTIVE IN ECM | ECM | DEFAULT ECM STATE |
|---|---|---|---|---|
| INPUT CONTROL AND ADJUST | ||||
| AC- and DC-coupled mode selection | Selected through VCMO (Pin C2) | Yes | Not available | N/A |
| Input full-scale range adjust | Selected through FSR (Pin Y3) | No | Selected through the Configuration Register (Addr: 3h and Bh) | Mid FSR value |
| Input offset adjust setting | Not available | N/A | Selected through the Configuration Register (Addr: 2h and Ah) | Offset = 0 mV |
| Low-sampling power-saving mode | Selected through LSPSM (Pin V4) | Yes | Not available | N/A |
| DES / Non-DES mode selection | Selected through DES (Pin V5) | No | Selected through the DES bit (Addr: 0h; Bit: 7) | Non-DES mode |
| DES mode input selection | Not available | N/A | Selected through the DEQ, DIQ bits (Addr: 0h; Bits: 6:5) | N/A |
| DESCLKIQ mode | Not available | N/A | Selected through the DCK bit (Addr: Eh; Bit: 6) | N/A |
| DES timing adjust | Not available | N/A | Selected through the DES Timing Adjust Reg (Addr: 7h) | Mid skew offset |
| Sampling clock phase adjust | Not available | N/A | Selected through the Configuration Register (Addr: Ch and Dh) | tAD adjust disabled |
| OUTPUT CONTROL AND ADJUST | ||||
| DDR clock phase selection | Selected through DDRPh (Pin W4) | No | Selected through the DPS bit (Addr: 0h; Bit: 14) | 0° mode |
| DDR / SDR DCLK selection | Not available | N/A | Selected through the SDR bit (Addr: 0h; Bit: 2) | DDR mode |
| SDR rising / falling DCLK Selection | Not available | N/A | Selected through the DPS bit (Addr: 0h; Bit: 14) | N/A |
| LVDS differential voltage amplitude selection | Higher amplitude only | N/A | Selected through the OVS bit (Addr: 0h; Bit: 13) | Higher amplitude |
| LVDS common-mode voltage amplitude selection | Selected through VBG (Pin B1) | Yes | Not available | N/A |
| Output formatting selection | Offset binary only | N/A | Selected through the 2SC bit (Addr: 0h; Bit: 4) | Offset binary |
| Test pattern mode at output | Selected through TPM (Pin A4) | No | Selected through the TPM bit (Addr: 0h; Bit: 12) | TPM disabled |
| Demux/Non-demux mode selection | Selected through NDM (Pin A5) | Yes | Not available | N/A |
| AutoSync | Not available | N/A | Selected through the Configuration Register (Addr: Eh) | primary mode, RCOut1, RCOut2 disabled |
| DCLK reset | Not available | N/A | Selected through the Configuration Register (Addr: Eh; Bit: 0) | DCLK reset disabled |
| Time stamp | Not available | N/A | Selected through the TSE bit (Addr: 0h; Bit: 3) | Time stamp disabled |
| CALIBRATION | ||||
| On-command calibration | Selected through CAL (Pin D6) | Yes | Selected through the CAL bit (Addr: 0h; Bit: 15) | N/A (CAL = 0) |
| Calibration Adjust | Not available | N/A | Selected through the Configuration Register (Addr: 4h) | tCAL |
| Read/Write calibration settings | Not available | N/A | Selected through the SSC bit (Addr: 4h; Bit: 7) | R/W calibration values disabled |
| POWER-DOWN | ||||
| Power down I channel | Selected through PDI (Pin U3) | Yes | Selected through the PDI bit (Addr: 0h; Bit: 11) | I-channel operational |
| Power down Q channel | Selected through PDQ (Pin V3) | Yes | Selected through the PDQ bit (Addr: 0h; Bit: 10) | Q-channel operational |