OMAP3530

Name: OMAP3530
Brand: TI
SKU: OMAP3530
Price: 33.792 USD

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應用處理器

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數據表

document-pdfAcrobat OMAP3530 and OMAP3525 Applications Processors 數據表 (Rev. H) (英語)

勘誤

document-pdfAcrobat
OMAP3530/25/15/03 Applications Processor Silicon Errata (Rev. F) (英語)

OMAP3530

正在供貨

數據表

立即訂購

產品詳情

CPU

1 Arm Cortex-A8

Frequency (MHz)

720

Coprocessors

C64x DSP

Display type

2 LCD, Parallel Digital Output, Support for Remote Frame Buffer, Up to 24-Bit RGB Compatible

Operating system

Linux, RTOS

Security

Secure boot

Rating

Catalog

Power supply solution

TPS65921, TPS65950

Operating temperature range (°C)

-40 to 105

CPU

1 Arm Cortex-A8

Frequency (MHz)

720

Coprocessors

C64x DSP

Display type

2 LCD, Parallel Digital Output, Support for Remote Frame Buffer, Up to 24-Bit RGB Compatible

Operating system

Linux, RTOS

Security

Secure boot

Rating

Catalog

Power supply solution

TPS65921, TPS65950

Operating temperature range (°C)

-40 to 105

FCCSP (CBB)

515

144 mm2 12 x 12

FCCSP (CUS)

423

256 mm2 16 x 16

OMAP3530 and OMAP3525 Devices:
- OMAP? 3 Architecture
- MPU Subsystem
  - Up to 720-MHz ARM? Cortex?-A8 Core
  - NEON? SIMD Coprocessor
- High-Performance Image, Video, Audio (IVA2.2?) Accelerator Subsystem
  - Up to 520-MHz TMS320C64x+? DSP Core
  - Enhanced Direct Memory Access (EDMA) Controller (128 Independent Channels)
  - Video Hardware Accelerators
- PowerVR? SGX? Graphics Accelerator (OMAP3530 Device Only)
  - Tile-Based Architecture Delivering up to 10 MPoly/sec
  - Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality
  - Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0
  - Fine-Grained Task Switching, Load Balancing, and Power Management
  - Programmable High-Quality Image Anti-Aliasing
- Fully Software-Compatible with C64x and ARM9?
- Commercial and Extended Temperature Grades
Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+ DSP Core
- Eight Highly Independent Functional Units
  - Six ALUs (32- and 40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
  - Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
- Load-Store Architecture with Nonaligned Support
- 64 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Additional C64x+ Enhancements
  - Protected Mode Operation
  - Exceptions Support for Error Detection and Program Redirection
  - Hardware Support for Modulo Loop Operation
C64x+ L1 and L2 Memory Architecture
- 32KB of L1P Program RAM and Cache (Direct Mapped)
- 80KB of L1D Data RAM and Cache (2-Way Set-Associative)
- 64KB of L2 Unified Mapped RAM and Cache (4-Way Set-Associative)
- 32KB of L2 Shared SRAM and 16KB of L2 ROM
C64x+ Instruction Set Features
- Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
- 8-Bit Overflow Protection
- Bit Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- Compact 16-Bit Instructions
- Additional Instructions to Support Complex Multiplies
ARM Cortex-A8 Core
- ARMv7 Architecture
  - TrustZone?
  - Thumb?-2
  - MMU Enhancements
- In-Order, Dual-Issue, Superscalar Microprocessor Core
- NEON Multimedia Architecture
- Over 2x Performance of ARMv6 SIMD
- Supports Both Integer and Floating-Point SIMD
- Jazelle? RCT Execution Environment Architecture
- Dynamic Branch Prediction with Branch Target Address Cache, Global History Buffer, and 8-Entry Return Stack
- Embedded Trace Macrocell (ETM) Support for Noninvasive Debug
ARM Cortex-A8 Memory Architecture:
- 16-KB Instruction Cache (4-Way Set-Associative)
- 16-KB Data Cache (4-Way Set-Associative)
- 256-KB L2 Cache
112KB of ROM
64KB of Shared SRAM
Endianess:
- ARM Instructions – Little Endian
- ARM Data – Configurable
- DSP Instruction and Data - Little Endian
External Memory Interfaces:
- SDRAM Controller (SDRC)
  - 16- and 32-Bit Memory Controller with 1GB of Total Address Space
  - Interfaces to Low-Power Double Data Rate (LPDDR) SDRAM
  - SDRAM Memory Scheduler (SMS) and Rotation Engine
- General Purpose Memory Controller (GPMC)
  - 16-Bit-Wide Multiplexed Address and Data Bus
  - Up to 8 Chip-Select Pins with 128-MB Address Space per Chip-Select Pin
  - Glueless Interface to NOR Flash, NAND Flash (with ECC Hamming Code Calculation), SRAM, and Pseudo-SRAM
  - Flexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, and so forth)
  - Nonmultiplexed Address and Data Mode (Limited 2-KB Address Space)
System Direct Memory Access (sDMA) Controller (32 Logical Channels with Configurable Priority)
Camera Image Signal Processor (ISP)
- CCD and CMOS Imager Interface
- Memory Data Input
- BT.601 (8-Bit) and BT.656 (10-Bit) Digital YCbCr 4:2:2 Interface
- Glueless Interface to Common Video Decoders
- Resize Engine
  - Resize Images From 1/4x to 4x
  - Separate Horizontal and Vertical Control
Display Subsystem
- Parallel Digital Output
  - Up to 24-Bit RGB
  - HD Maximum Resolution
  - Supports Up to 2 LCD Panels
  - Support for Remote Frame Buffer Interface (RFBI) LCD Panels
- 2 10-Bit Digital-to-Analog Converters (DACs) Supporting:
  - Composite NTSC and PAL Video
  - Luma and Chroma Separate Video (S-Video)
- Rotation 90-, 180-, and 270-Degrees
- Resize Images From 1/4x to 8x
- Color Space Converter
- 8-Bit Alpha Blending
Serial Communication
- 5 Multichannel Buffered Serial Ports (McBSPs)
  - 512-Byte Transmit and Receive Buffer (McBSP1, McBSP3, McBSP4, and McBSP5)
  - 5-KB Transmit and Receive Buffer (McBSP2)
  - SIDETONE Core Support (McBSP2 and McBSP3 Only) For Filter, Gain, and Mix Operations
  - Direct Interface to I2S and PCM Device and TDM Buses
  - 128-Channel Transmit and Receive Mode
- Four Master or Slave Multichannel Serial Port Interface (McSPI) Ports
- High-, Full-, and Low-Speed USB OTG Subsystem (12- and 8-Pin ULPI Interface)
- High-, Full-, and Low-Speed Multiport USB Host Subsystem
  - 12- and 8-Pin ULPI Interface or 6-, 4-, and 3-Pin Serial Interface
  - Supports Transceiverless Link Logic (TLL)
- One HDQ?/1-Wire? Interface
- Three UARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes)
- Three Master and Slave High-Speed Inter-Integrated Circuit (I²C) Controllers
Removable Media Interfaces:
- Three Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)
Comprehensive Power, Reset, and Clock Management
- SmartReflex? Technology
- Dynamic Voltage and Frequency Scaling (DVFS)
Test Interfaces
- IEEE 1149.1 (JTAG) Boundary-Scan Compatible
- ETM Interface
- Serial Data Transport Interface (SDTI)
12 32-Bit General-Purpose Timers
2 32-Bit Watchdog Timers
1 32-Bit 32-kHz Sync Timer
Up to 188 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
65-nm CMOS Technologies
Package-On-Package (POP) Implementation for Memory Stacking (Not Available in CUS Package)
Discrete Memory Interface (Not Available in CBC Package)
Packages:
- 515-pin s-PBGA Package (CBB Suffix),
  .5-mm Ball Pitch (Top), .4-mm Ball Pitch (Bottom)
- 515-pin s-PBGA Package (CBC Suffix),
  .65-mm Ball Pitch (Top), .5-mm Ball Pitch (Bottom)
- 423-pin s-PBGA Package (CUS Suffix),
  .65-mm Ball Pitch
1.8-V I/O and 3.0-V (MMC1 Only),
0.985-V to 1.35-V Adaptive Processor Core Voltage
0.985-V to 1.35-V Adaptive Core Logic Voltage
Note: These are default Operating Performance Point (OPP) voltages and could be optimized to lower values using SmartReflex AVS.

OMAP3530 and OMAP3525 Devices:
- OMAP? 3 Architecture
- MPU Subsystem
  - Up to 720-MHz ARM? Cortex?-A8 Core
  - NEON? SIMD Coprocessor
- High-Performance Image, Video, Audio (IVA2.2?) Accelerator Subsystem
  - Up to 520-MHz TMS320C64x+? DSP Core
  - Enhanced Direct Memory Access (EDMA) Controller (128 Independent Channels)
  - Video Hardware Accelerators
- PowerVR? SGX? Graphics Accelerator (OMAP3530 Device Only)
  - Tile-Based Architecture Delivering up to 10 MPoly/sec
  - Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality
  - Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0
  - Fine-Grained Task Switching, Load Balancing, and Power Management
  - Programmable High-Quality Image Anti-Aliasing
- Fully Software-Compatible with C64x and ARM9?
- Commercial and Extended Temperature Grades
Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+ DSP Core
- Eight Highly Independent Functional Units
  - Six ALUs (32- and 40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
  - Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
- Load-Store Architecture with Nonaligned Support
- 64 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Additional C64x+ Enhancements
  - Protected Mode Operation
  - Exceptions Support for Error Detection and Program Redirection
  - Hardware Support for Modulo Loop Operation
C64x+ L1 and L2 Memory Architecture
- 32KB of L1P Program RAM and Cache (Direct Mapped)
- 80KB of L1D Data RAM and Cache (2-Way Set-Associative)
- 64KB of L2 Unified Mapped RAM and Cache (4-Way Set-Associative)
- 32KB of L2 Shared SRAM and 16KB of L2 ROM
C64x+ Instruction Set Features
- Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
- 8-Bit Overflow Protection
- Bit Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- Compact 16-Bit Instructions
- Additional Instructions to Support Complex Multiplies
ARM Cortex-A8 Core
- ARMv7 Architecture
  - TrustZone?
  - Thumb?-2
  - MMU Enhancements
- In-Order, Dual-Issue, Superscalar Microprocessor Core
- NEON Multimedia Architecture
- Over 2x Performance of ARMv6 SIMD
- Supports Both Integer and Floating-Point SIMD
- Jazelle? RCT Execution Environment Architecture
- Dynamic Branch Prediction with Branch Target Address Cache, Global History Buffer, and 8-Entry Return Stack
- Embedded Trace Macrocell (ETM) Support for Noninvasive Debug
ARM Cortex-A8 Memory Architecture:
- 16-KB Instruction Cache (4-Way Set-Associative)
- 16-KB Data Cache (4-Way Set-Associative)
- 256-KB L2 Cache
112KB of ROM
64KB of Shared SRAM
Endianess:
- ARM Instructions – Little Endian
- ARM Data – Configurable
- DSP Instruction and Data - Little Endian
External Memory Interfaces:
- SDRAM Controller (SDRC)
  - 16- and 32-Bit Memory Controller with 1GB of Total Address Space
  - Interfaces to Low-Power Double Data Rate (LPDDR) SDRAM
  - SDRAM Memory Scheduler (SMS) and Rotation Engine
- General Purpose Memory Controller (GPMC)
  - 16-Bit-Wide Multiplexed Address and Data Bus
  - Up to 8 Chip-Select Pins with 128-MB Address Space per Chip-Select Pin
  - Glueless Interface to NOR Flash, NAND Flash (with ECC Hamming Code Calculation), SRAM, and Pseudo-SRAM
  - Flexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, and so forth)
  - Nonmultiplexed Address and Data Mode (Limited 2-KB Address Space)
System Direct Memory Access (sDMA) Controller (32 Logical Channels with Configurable Priority)
Camera Image Signal Processor (ISP)
- CCD and CMOS Imager Interface
- Memory Data Input
- BT.601 (8-Bit) and BT.656 (10-Bit) Digital YCbCr 4:2:2 Interface
- Glueless Interface to Common Video Decoders
- Resize Engine
  - Resize Images From 1/4x to 4x
  - Separate Horizontal and Vertical Control
Display Subsystem
- Parallel Digital Output
  - Up to 24-Bit RGB
  - HD Maximum Resolution
  - Supports Up to 2 LCD Panels
  - Support for Remote Frame Buffer Interface (RFBI) LCD Panels
- 2 10-Bit Digital-to-Analog Converters (DACs) Supporting:
  - Composite NTSC and PAL Video
  - Luma and Chroma Separate Video (S-Video)
- Rotation 90-, 180-, and 270-Degrees
- Resize Images From 1/4x to 8x
- Color Space Converter
- 8-Bit Alpha Blending
Serial Communication
- 5 Multichannel Buffered Serial Ports (McBSPs)
  - 512-Byte Transmit and Receive Buffer (McBSP1, McBSP3, McBSP4, and McBSP5)
  - 5-KB Transmit and Receive Buffer (McBSP2)
  - SIDETONE Core Support (McBSP2 and McBSP3 Only) For Filter, Gain, and Mix Operations
  - Direct Interface to I2S and PCM Device and TDM Buses
  - 128-Channel Transmit and Receive Mode
- Four Master or Slave Multichannel Serial Port Interface (McSPI) Ports
- High-, Full-, and Low-Speed USB OTG Subsystem (12- and 8-Pin ULPI Interface)
- High-, Full-, and Low-Speed Multiport USB Host Subsystem
  - 12- and 8-Pin ULPI Interface or 6-, 4-, and 3-Pin Serial Interface
  - Supports Transceiverless Link Logic (TLL)
- One HDQ?/1-Wire? Interface
- Three UARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes)
- Three Master and Slave High-Speed Inter-Integrated Circuit (I²C) Controllers
Removable Media Interfaces:
- Three Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)
Comprehensive Power, Reset, and Clock Management
- SmartReflex? Technology
- Dynamic Voltage and Frequency Scaling (DVFS)
Test Interfaces
- IEEE 1149.1 (JTAG) Boundary-Scan Compatible
- ETM Interface
- Serial Data Transport Interface (SDTI)
12 32-Bit General-Purpose Timers
2 32-Bit Watchdog Timers
1 32-Bit 32-kHz Sync Timer
Up to 188 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
65-nm CMOS Technologies
Package-On-Package (POP) Implementation for Memory Stacking (Not Available in CUS Package)
Discrete Memory Interface (Not Available in CBC Package)
Packages:
- 515-pin s-PBGA Package (CBB Suffix),
  .5-mm Ball Pitch (Top), .4-mm Ball Pitch (Bottom)
- 515-pin s-PBGA Package (CBC Suffix),
  .65-mm Ball Pitch (Top), .5-mm Ball Pitch (Bottom)
- 423-pin s-PBGA Package (CUS Suffix),
  .65-mm Ball Pitch
1.8-V I/O and 3.0-V (MMC1 Only),
0.985-V to 1.35-V Adaptive Processor Core Voltage
0.985-V to 1.35-V Adaptive Core Logic Voltage
Note: These are default Operating Performance Point (OPP) voltages and could be optimized to lower values using SmartReflex AVS.

OMAP3530 and OMAP3525 devices are based on the enhanced OMAP 3 architecture.

The OMAP 3 architecture is designed to provide best-in-class video, image, and graphics processing sufficient to support the following:

Streaming video
Video conferencing
High-resolution still image

The device supports high-level operating systems (HLOSs), such as:

Linux®
Windows® CE
Android™

This OMAP device includes state-of-the-art power-management techniques required for high-performance mobile products.

The following subsystems are part of the device:

Microprocessor unit (MPU) subsystem based on the ARM Cortex-A8 microprocessor
IVA2.2 subsystem with a C64x+ digital signal processor (DSP) core
PowerVR SGX subsystem for 3D graphics acceleration to support display (OMAP3530 device only)
Camera image signal processor (ISP) that supports multiple formats and interfacing options connected to a wide variety of image sensors
Display subsystem with a wide variety of features for multiple concurrent image manipulation, and a programmable interface supporting a wide variety of displays. The display subsystem also supports NTSC and PAL video out.
Level 3 (L3) and level 4 (L4) interconnects that provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripherals

The device also offers:

A comprehensive power- and clock-management scheme that enables high-performance, low-power operation, and ultralow-power standby features. The device also supports SmartReflex adaptative voltage control. This power-management technique for automatic control of the operating voltage of a module reduces the active power consumption.
Memory-stacking feature using the package-on-package (POP) implementation (CBB and CBC packages only)

OMAP3530 and OMAP3525 devices are available in a 515-pin s-PBGA package (CBB suffix), 515-pin s-PBGA package (CBC suffix), and a 423-pin s-PBGA package (CUS suffix). Some features of the CBB and CBC packages are not available in the CUS package. (See Table 1-1 for package differences).

This data manual presents the electrical and mechanical specifications for the OMAP3530 and OMAP3525 applications processors. The information in this data manual applies to both the commercial and extended temperature versions of the OMAP3530 and OMAP3525 applications processors unless otherwise indicated. This data manual consists of the following sections:

Section 2: Terminal Description: assignment, electrical characteristics, multiplexing, and functional description
Section 3: Electrical Characteristics: power domains, operating conditions, power consumption, and DC characteristics
Section 4: Clock Specifications input and output clocks, DPLL and DLL
Section 5: Video Dac Specifications
Section 6: Timing Requirements and Switching Characteristics
Section 7: Package Characteristics: thermal characteristics, device nomenclature, and mechanical data for available packaging

OMAP3530 and OMAP3525 devices are based on the enhanced OMAP 3 architecture.

The OMAP 3 architecture is designed to provide best-in-class video, image, and graphics processing sufficient to support the following:

Streaming video
Video conferencing
High-resolution still image

The device supports high-level operating systems (HLOSs), such as:

Linux®
Windows® CE
Android™

This OMAP device includes state-of-the-art power-management techniques required for high-performance mobile products.

The following subsystems are part of the device:

Microprocessor unit (MPU) subsystem based on the ARM Cortex-A8 microprocessor
IVA2.2 subsystem with a C64x+ digital signal processor (DSP) core
PowerVR SGX subsystem for 3D graphics acceleration to support display (OMAP3530 device only)
Camera image signal processor (ISP) that supports multiple formats and interfacing options connected to a wide variety of image sensors
Display subsystem with a wide variety of features for multiple concurrent image manipulation, and a programmable interface supporting a wide variety of displays. The display subsystem also supports NTSC and PAL video out.
Level 3 (L3) and level 4 (L4) interconnects that provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripherals

The device also offers:

A comprehensive power- and clock-management scheme that enables high-performance, low-power operation, and ultralow-power standby features. The device also supports SmartReflex adaptative voltage control. This power-management technique for automatic control of the operating voltage of a module reduces the active power consumption.
Memory-stacking feature using the package-on-package (POP) implementation (CBB and CBC packages only)

Section 2: Terminal Description: assignment, electrical characteristics, multiplexing, and functional description
Section 3: Electrical Characteristics: power domains, operating conditions, power consumption, and DC characteristics
Section 4: Clock Specifications input and output clocks, DPLL and DLL
Section 5: Video Dac Specifications
Section 6: Timing Requirements and Switching Characteristics
Section 7: Package Characteristics: thermal characteristics, device nomenclature, and mechanical data for available packaging

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	類型	標題		下載最新的英語版本	日期
*	數據表	OMAP3530 and OMAP3525 Applications Processors 數據表 (Rev. H)			2013年 10月 10日
*	勘誤表	OMAP3530/25/15/03 Applications Processor Silicon Errata (Rev. F)			2010年 10月 12日
	用戶指南	SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V)			2020年 6月 1日
	應用手冊	(Cancelled - see the B revision, create by mistake 14-may-2009) (Rev. C)	PDF \| HTML		2020年 3月 3日
	應用手冊	OMAP3530/25/15/03, DM3730/25, AM3715/03 CBB, CBC and CUS reflow profiles			2019年 3月 20日
	應用手冊	PCB Assembly Guidelines for 0.4mm Package-On-Package (PoP) Packages, Part II (Rev. A)			2013年 11月 1日
	更多文獻資料	Picture it: DSPs in medical imaging (Rev. C)			2013年 7月 12日
	用戶指南	Delta for OMAP35x Technical Reference Manual Version X to Version Y (Rev. Y)			2012年 12月 10日
	用戶指南	OMAP35x Technical Reference Manual (Rev. Y)			2012年 12月 10日
	應用手冊	Introduction to TMS320C6000 DSP Optimization			2011年 10月 6日
	應用手冊	使用 TPS65023 為 OMAP?3 供電：設計指南 (Rev. B)			2010年 10月 8日
	用戶指南	使用 TPS65950 為 OMAP?3 供電：設計用戶指南 (Rev. C)		英語版 (Rev.C)	2010年 10月 8日
	應用手冊	PCB Assembly Guidelines for 0.5mm Package-on-Package Apps Processors, Part II			2010年 6月 23日
	應用手冊	PCB Design Guidelines for 0.5mm Package-On-Package Apps Processors, Part I			2010年 6月 23日
	應用手冊	Migrating from OMAP3530 to AM37x			2010年 6月 3日
	應用手冊	Migrating from OMAP3530 to AM35x			2010年 5月 24日
	應用手冊	OMAP3530 Easy CUS Package PCB Escape Routing (Rev. A)			2010年 3月 25日
	用戶指南	OMAP35x Peripherals Overview Reference Guide (Rev. A)			2010年 1月 20日
	應用手冊	OMAP3530 Power Consumption Summary			2010年 1月 8日
	應用手冊	OMAP35x Linux PSP Data Sheet			2009年 10月 16日
	設計指南	Powering OMAP35x with TPS65073x			2009年 10月 13日
	應用手冊	Running a TMS320C64x+ Codec Across TMS320C64x+ Based DSP Platforms			2009年 9月 24日
	應用手冊	Ultrasound Scan Conversion on TI's C64x+ DSPs			2009年 4月 3日
	應用手冊	OMAP35x 0.65mm Pitch Layout Methods (Rev. B)			2008年 6月 26日

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軟件開發套件 (SDK)

ANDROIDSDK-SITARA — 適用于 Sitara 微處理器的 Android 開發套件

雖然起初專為移動手持終端而設計，Android 操作系統仍允許嵌入式應用的設計人員輕松為產品增加高級操作系統。與 Google 聯合開發的 Android 是一套可立即實現集成和生產的全面操作系統。

Android 操作系統的亮點包括：

完整的開放源碼軟件解決方案
基于 Linux
針對商業開發的簡潔許可條款 (Apache)
包含一個完整的應用程序框架
允許通過 Java 輕松集成客戶開發的應用程序
開箱即用的多媒體、圖形和圖形用戶界面
如今已形成龐大的 Android 和應用程序開發人員社區

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軟件編解碼器

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DSP 與 ARM 軟件和硬件開發套件 - 所有可用的 SDK
如何將編解碼器集成至 DVSDK
DaVinci 和 OMAP 軟件入門教程
基于 TI C64x+ 的器件的編解碼器性能測量
TI E2E? 社區

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軟件編解碼器

OMAP35XCODECS — 用于 OMAP35x 的編解碼器 - 軟件和文檔

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into audio, video and voice applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes (...)

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基于 Arm 的處理器

OMAP3503 — Sitara 處理器：Arm Cortex-A8、LPDDR

OMAP3515 — Sitara 處理器：Arm Cortex-A8、3D 圖形、LPDDR

OMAP3525 — 應用處理器

OMAP3530 — 應用處理器

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軟件編程工具

FLASHTOOL — 用于 AM35x、AM37x、DM37x 和 OMAP35x 器件的 FlashTool

Flash Tool is a Windows-based application that can be used to transfer binary images from a host PC to TI Sitara AM35x, AM37x, DM37x and OMAP35x target platforms.

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