產(chǎn)品詳情

CPU 1 Arm Cortex-A8 Frequency (MHz) 720 Display type 1 LCD Operating system Linux, RTOS Rating Catalog Power supply solution TPS65921, TPS65950 Operating temperature range (°C) -40 to 105
CPU 1 Arm Cortex-A8 Frequency (MHz) 720 Display type 1 LCD Operating system Linux, RTOS Rating Catalog Power supply solution TPS65921, TPS65950 Operating temperature range (°C) -40 to 105
FCCSP (CBB) 515 144 mm2 12 x 12 FCCSP (CUS) 423 256 mm2 16 x 16
  • OMAP3 Devices:
    • OMAP? 3 Architecture
    • MPU Subsystem
      • Up to 720-MHz ARM? Cortex?-A8 Core
      • NEON? SIMD Coprocessor
    • PowerVR? SGX? Graphics Accelerator
      • Tile-Based Architecture Delivering up to 1 MPoly/sec
      • Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality
      • Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0
      • Fine-Grained Task Switching, Load Balancing, and Power Management
      • Programmable High-Quality Image Anti-Aliasing
    • Fully Software-Compatible with ARM9?
    • Commercial and Extended Temperature Grades
  • ARM Cortex-A8 Core
    • ARMv7 Architecture
      • TrustZone?
      • Thumb?-2
      • MMU Enhancements
    • In-Order, Dual-Issue, Superscalar Microprocessor Core
    • NEON Multimedia Architecture
    • Over 2x Performance of ARMv6 SIMD
    • Supports Both Integer and Floating-Point SIMD
    • Jazelle? RCT Execution Environment Architecture
    • Dynamic Branch Prediction with Branch Target Address Cache, Global History Buffer, and 8-Entry Return Stack
    • Embedded Trace Macrocell (ETM) Support for Noninvasive Debug
  • ARM Cortex-A8 Memory Architecture:
    • -KB Instruction Cache (4-Way Set-Associative)
    • -KB Data Cache (4-Way Set-Associative)
    • -KB L2 Cache
  • 112KB of ROM
  • 64KB of Shared SRAM
  • Endianess:
    • ARM Instructions – Little Endian
    • ARM Data – Configurable
  • External Memory Interfaces:
    • General Purpose Memory Controller (GPMC)
      • 16-Bit-Wide Multiplexed Address and Data Bus
      • Up to 8 Chip-Select Pins with 128-MB Address Space per Chip-Select Pin
      • Glueless Interface to NOR Flash, NAND Flash (with ECC Hamming Code Calculation), SRAM, and Pseudo-SRAM
      • Flexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, and so forth)
      • Nonmultiplexed Address and Data Mode (Limited 2-KB Address Space)
  • System Direct Memory Access (sDMA) Controller (32 Logical Channels with Configurable Priority)
  • Camera Image Signal Processor (ISP)
    • CCD and CMOS Imager Interface
    • Memory Data Input
    • BT.601 (8-Bit) and BT.656 (10-Bit) Digital YCbCr 4:2:2 Interface
    • Glueless Interface to Common Video Decoders
    • Resize Engine
      • Resize Images From 1/4x to 4x
      • Separate Horizontal and Vertical Control
  • Display Subsystem
    • Parallel Digital Output
      • Up to 24-Bit RGB
      • HD Maximum Resolution
      • Supports Up to 2 LCD Panels
      • Support for Remote Frame Buffer Interface (RFBI) LCD Panels
    • 2 10-Bit Digital-to-Analog Converters (DACs) Supporting:
      • Composite NTSC and PAL Video
      • Luma and Chroma Separate Video (S-Video)
    • Rotation 90-, 180-, and 270-Degrees
    • Resize Images From 1/4x to 8x
    • Color Space Converter
    • 8-Bit Alpha Blending
  • Serial Communication
    • 5 Multichannel Buffered Serial Ports (McBSPs)
      • 512-Byte Transmit and Receive Buffer (McBSP1, McBSP3, McBSP4, and McBSP5)
      • 5-KB Transmit and Receive Buffer (McBSP2)
      • SIDETONE Core Support (McBSP2 and McBSP3 Only) For Filter, Gain, and Mix Operations
      • Direct Interface to I2S and PCM Device and TDM Buses
      • 128-Channel Transmit and Receive Mode
    • Four Master or Slave Multichannel Serial Port Interface (McSPI) Ports
    • High-, Full-, and Low-Speed USB OTG Subsystem (12- and 8-Pin ULPI Interface)
    • High-, Full-, and Low-Speed Multiport USB Host Subsystem
      • 12- and 8-Pin ULPI Interface or 6-, 4-, and 3-Pin Serial Interface
    • One HDQ?/1-Wire? Interface
    • UARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes)
    • Three Master and Slave High-Speed Inter-Integrated Circuit (I2C) Controllers
  • Removable Media Interfaces:
    • Three Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)
  • Comprehensive Power, Reset, and Clock Management
    • SmartReflex? Technology
    • Dynamic Voltage and Frequency Scaling (DVFS)
  • Test Interfaces
    • IEEE 1149.1 (JTAG) Boundary-Scan Compatible
    • ETM Interface
    • Serial Data Transport Interface (SDTI)
  • 12 32-Bit General-Purpose Timers
  • 2 32-Bit Watchdog Timers
  • 1 32-Bit 32-kHz Sync Timer
  • Up to General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
  • 5-nm CMOS Technologies
  • Package-On-Package (POP) Implementation for Memory Stacking (Not Available in CUS Package)
  • Discrete Memory Interface
  • Packages:
  • 1.8-V I/O and 3.0-V (MMC1 Only),


    Note: These are default Operating Performance Point (OPP) voltages and could be optimized to lower values using SmartReflex AVS.
  • OMAP3 Devices:
    • OMAP? 3 Architecture
    • MPU Subsystem
      • Up to 720-MHz ARM? Cortex?-A8 Core
      • NEON? SIMD Coprocessor
    • PowerVR? SGX? Graphics Accelerator
      • Tile-Based Architecture Delivering up to 1 MPoly/sec
      • Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality
      • Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0
      • Fine-Grained Task Switching, Load Balancing, and Power Management
      • Programmable High-Quality Image Anti-Aliasing
    • Fully Software-Compatible with ARM9?
    • Commercial and Extended Temperature Grades
  • ARM Cortex-A8 Core
    • ARMv7 Architecture
      • TrustZone?
      • Thumb?-2
      • MMU Enhancements
    • In-Order, Dual-Issue, Superscalar Microprocessor Core
    • NEON Multimedia Architecture
    • Over 2x Performance of ARMv6 SIMD
    • Supports Both Integer and Floating-Point SIMD
    • Jazelle? RCT Execution Environment Architecture
    • Dynamic Branch Prediction with Branch Target Address Cache, Global History Buffer, and 8-Entry Return Stack
    • Embedded Trace Macrocell (ETM) Support for Noninvasive Debug
  • ARM Cortex-A8 Memory Architecture:
    • -KB Instruction Cache (4-Way Set-Associative)
    • -KB Data Cache (4-Way Set-Associative)
    • -KB L2 Cache
  • 112KB of ROM
  • 64KB of Shared SRAM
  • Endianess:
    • ARM Instructions – Little Endian
    • ARM Data – Configurable
  • External Memory Interfaces:
    • General Purpose Memory Controller (GPMC)
      • 16-Bit-Wide Multiplexed Address and Data Bus
      • Up to 8 Chip-Select Pins with 128-MB Address Space per Chip-Select Pin
      • Glueless Interface to NOR Flash, NAND Flash (with ECC Hamming Code Calculation), SRAM, and Pseudo-SRAM
      • Flexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, and so forth)
      • Nonmultiplexed Address and Data Mode (Limited 2-KB Address Space)
  • System Direct Memory Access (sDMA) Controller (32 Logical Channels with Configurable Priority)
  • Camera Image Signal Processor (ISP)
    • CCD and CMOS Imager Interface
    • Memory Data Input
    • BT.601 (8-Bit) and BT.656 (10-Bit) Digital YCbCr 4:2:2 Interface
    • Glueless Interface to Common Video Decoders
    • Resize Engine
      • Resize Images From 1/4x to 4x
      • Separate Horizontal and Vertical Control
  • Display Subsystem
    • Parallel Digital Output
      • Up to 24-Bit RGB
      • HD Maximum Resolution
      • Supports Up to 2 LCD Panels
      • Support for Remote Frame Buffer Interface (RFBI) LCD Panels
    • 2 10-Bit Digital-to-Analog Converters (DACs) Supporting:
      • Composite NTSC and PAL Video
      • Luma and Chroma Separate Video (S-Video)
    • Rotation 90-, 180-, and 270-Degrees
    • Resize Images From 1/4x to 8x
    • Color Space Converter
    • 8-Bit Alpha Blending
  • Serial Communication
    • 5 Multichannel Buffered Serial Ports (McBSPs)
      • 512-Byte Transmit and Receive Buffer (McBSP1, McBSP3, McBSP4, and McBSP5)
      • 5-KB Transmit and Receive Buffer (McBSP2)
      • SIDETONE Core Support (McBSP2 and McBSP3 Only) For Filter, Gain, and Mix Operations
      • Direct Interface to I2S and PCM Device and TDM Buses
      • 128-Channel Transmit and Receive Mode
    • Four Master or Slave Multichannel Serial Port Interface (McSPI) Ports
    • High-, Full-, and Low-Speed USB OTG Subsystem (12- and 8-Pin ULPI Interface)
    • High-, Full-, and Low-Speed Multiport USB Host Subsystem
      • 12- and 8-Pin ULPI Interface or 6-, 4-, and 3-Pin Serial Interface
    • One HDQ?/1-Wire? Interface
    • UARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes)
    • Three Master and Slave High-Speed Inter-Integrated Circuit (I2C) Controllers
  • Removable Media Interfaces:
    • Three Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)
  • Comprehensive Power, Reset, and Clock Management
    • SmartReflex? Technology
    • Dynamic Voltage and Frequency Scaling (DVFS)
  • Test Interfaces
    • IEEE 1149.1 (JTAG) Boundary-Scan Compatible
    • ETM Interface
    • Serial Data Transport Interface (SDTI)
  • 12 32-Bit General-Purpose Timers
  • 2 32-Bit Watchdog Timers
  • 1 32-Bit 32-kHz Sync Timer
  • Up to General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
  • 5-nm CMOS Technologies
  • Package-On-Package (POP) Implementation for Memory Stacking (Not Available in CUS Package)
  • Discrete Memory Interface
  • Packages:
  • 1.8-V I/O and 3.0-V (MMC1 Only),


    Note: These are default Operating Performance Point (OPP) voltages and could be optimized to lower values using SmartReflex AVS.

devices are based on the enhanced OMAP 3 architecture.

The OMAP 3 architecture is designed to provide best-in-class video, image, and graphics processing sufficient to support the following:

  • Streaming video
  • Video conferencing
  • High-resolution still image

The device supports high-level operating systems (HLOSs), such as:

  • Linux®
  • Windows® CE
  • Android™

This OMAP device includes state-of-the-art power-management techniques required for high-performance mobile products.

The following subsystems are part of the device:

  • Microprocessor unit (MPU) subsystem based on the ARM Cortex-A8 microprocessor
  • PowerVR SGX subsystem for 3D graphics acceleration to support display (OMAP35 device only)
  • Camera image signal processor (ISP) that supports multiple formats and interfacing options connected to a wide variety of image sensors
  • Display subsystem with a wide variety of features for multiple concurrent image manipulation, and a programmable interface supporting a wide variety of displays. The display subsystem also supports NTSC and PAL video out.
  • Level 3 (L3) and level 4 (L4) interconnects that provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripherals

The device also offers:

  • A comprehensive power- and clock-management scheme that enables high-performance, low-power operation, and ultralow-power standby features. The device also supports SmartReflex adaptative voltage control. This power-management technique for automatic control of the operating voltage of a module reduces the active power consumption.
  • Memory-stacking feature using the package-on-package (POP) implementation (CBB and CBC packages only)

OMAP35 devices are available in a 515-pin s-PBGA package (CBB suffix), 515-pin s-PBGA package (CBC suffix), and a 423-pin s-PBGA package (CUS suffix). Some features of the CBB and CBC packages are not available in the CUS package. (See Table 1-1 for package differences).

This data manual presents the electrical and mechanical specifications for the OMAP35 applications processors. The information in this data manual applies to both the commercial and extended temperature versions of the OMAP35 applications processors unless otherwise indicated. This data manual consists of the following sections:

  • Section 2: Terminal Description: assignment, electrical characteristics, multiplexing, and functional description
  • Section 3: Electrical Characteristics: power domains, operating conditions, power consumption, and DC characteristics
  • Section 4: Clock Specifications input and output clocks, DPLL and DLL
  • Section 5: Video Dac Specifications
  • Section 6: Timing Requirements and Switching Characteristics
  • Section 7: Package Characteristics: thermal characteristics, device nomenclature, and mechanical data for available packaging

devices are based on the enhanced OMAP 3 architecture.

The OMAP 3 architecture is designed to provide best-in-class video, image, and graphics processing sufficient to support the following:

  • Streaming video
  • Video conferencing
  • High-resolution still image

The device supports high-level operating systems (HLOSs), such as:

  • Linux®
  • Windows® CE
  • Android™

This OMAP device includes state-of-the-art power-management techniques required for high-performance mobile products.

The following subsystems are part of the device:

  • Microprocessor unit (MPU) subsystem based on the ARM Cortex-A8 microprocessor
  • PowerVR SGX subsystem for 3D graphics acceleration to support display (OMAP35 device only)
  • Camera image signal processor (ISP) that supports multiple formats and interfacing options connected to a wide variety of image sensors
  • Display subsystem with a wide variety of features for multiple concurrent image manipulation, and a programmable interface supporting a wide variety of displays. The display subsystem also supports NTSC and PAL video out.
  • Level 3 (L3) and level 4 (L4) interconnects that provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripherals

The device also offers:

  • A comprehensive power- and clock-management scheme that enables high-performance, low-power operation, and ultralow-power standby features. The device also supports SmartReflex adaptative voltage control. This power-management technique for automatic control of the operating voltage of a module reduces the active power consumption.
  • Memory-stacking feature using the package-on-package (POP) implementation (CBB and CBC packages only)

OMAP35 devices are available in a 515-pin s-PBGA package (CBB suffix), 515-pin s-PBGA package (CBC suffix), and a 423-pin s-PBGA package (CUS suffix). Some features of the CBB and CBC packages are not available in the CUS package. (See Table 1-1 for package differences).

This data manual presents the electrical and mechanical specifications for the OMAP35 applications processors. The information in this data manual applies to both the commercial and extended temperature versions of the OMAP35 applications processors unless otherwise indicated. This data manual consists of the following sections:

  • Section 2: Terminal Description: assignment, electrical characteristics, multiplexing, and functional description
  • Section 3: Electrical Characteristics: power domains, operating conditions, power consumption, and DC characteristics
  • Section 4: Clock Specifications input and output clocks, DPLL and DLL
  • Section 5: Video Dac Specifications
  • Section 6: Timing Requirements and Switching Characteristics
  • Section 7: Package Characteristics: thermal characteristics, device nomenclature, and mechanical data for available packaging
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類型 標(biāo)題 下載最新的英語版本 日期
* 數(shù)據(jù)表 OMAP3515 and OMAP3503 Applications Processors 數(shù)據(jù)表 (Rev. H) 2013年 10月 10日
* 勘誤表 OMAP3530/25/15/03 Applications Processor Silicon Errata (Rev. F) 2010年 10月 12日
* 用戶指南 OMAP35x Technical Reference Manual (Rev. Y) 2012年 12月 19日
用戶指南 SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V) 2020年 6月 1日
應(yīng)用手冊(cè) (Cancelled - see the B revision, create by mistake 14-may-2009) (Rev. C) PDF | HTML 2020年 3月 3日
應(yīng)用手冊(cè) OMAP3530/25/15/03, DM3730/25, AM3715/03 CBB, CBC and CUS reflow profiles 2019年 3月 20日
用戶指南 How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS 2018年 9月 24日
應(yīng)用手冊(cè) PCB Assembly Guidelines for 0.4mm Package-On-Package (PoP) Packages, Part II (Rev. A) 2013年 11月 1日
用戶指南 Delta for OMAP35x Technical Reference Manual Version X to Version Y (Rev. Y) 2012年 12月 10日
應(yīng)用手冊(cè) 使用 TPS65023 為 OMAP?3 供電：設(shè)計(jì)指南 (Rev. B) 2010年 10月 8日
應(yīng)用手冊(cè) PCB Assembly Guidelines for 0.5mm Package-on-Package Apps Processors, Part II 2010年 6月 23日
應(yīng)用手冊(cè) PCB Design Guidelines for 0.5mm Package-On-Package Apps Processors, Part I 2010年 6月 23日
應(yīng)用手冊(cè) Migrating from OMAP3530 to AM37x 2010年 6月 3日
應(yīng)用手冊(cè) Migrating from OMAP3530 to AM35x 2010年 5月 24日
用戶指南 OMAP35x Peripherals Overview Reference Guide (Rev. A) 2010年 1月 20日
應(yīng)用手冊(cè) OMAP35x Linux PSP Data Sheet 2009年 10月 16日
設(shè)計(jì)指南 Powering OMAP35x with TPS65073x 2009年 10月 13日
應(yīng)用手冊(cè) Powering OMAP?3 With TPS6235x: Design-In Guide 2008年 12月 3日
應(yīng)用手冊(cè) OMAP35x 0.65mm Pitch Layout Methods (Rev. B) 2008年 6月 26日

設(shè)計(jì)和開發(fā)

如需其他信息或資源，請(qǐng)點(diǎn)擊以下任一標(biāo)題進(jìn)入詳情頁面查看（如有）。

調(diào)試探針

TMDSEMU200-U — XDS200 USB 調(diào)試探針

XDS200 是用于調(diào)試 TI 嵌入式器件的調(diào)試探針（仿真器）。? 與低成本的 XDS110 和高性能的 XDS560v2 相比，XDS200 在低成本和高性能之間實(shí)現(xiàn)了平衡。? 它在單個(gè)倉體中支持廣泛的標(biāo)準(zhǔn)（IEEE1149.1、IEEE1149.7、SWD）。所有 XDS 調(diào)試探針在所有具有嵌入式跟蹤緩沖器 (ETB) 的 Arm? 和 DSP 處理器中均支持內(nèi)核和系統(tǒng)跟蹤。??對(duì)于引腳上的內(nèi)核跟蹤，則需要使用?XDS560v2 PRO TRACE。

XDS200 通過 TI 20 引腳連接器（帶有適用于 TI 14 引腳、Arm Cortex? 10 引腳和 Arm 20 (...)

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調(diào)試探針

TMDSEMU560V2STM-U — XDS560? 軟件 v2 系統(tǒng)跟蹤 USB 調(diào)試探針

XDS560v2 是 XDS560™ 系列調(diào)試探針中性能非常出色的產(chǎn)品，同時(shí)支持傳統(tǒng) JTAG 標(biāo)準(zhǔn) (IEEE1149.1) 和 cJTAG (IEEE1149.7)。請(qǐng)注意，它不支持串行線調(diào)試 (SWD)。

所有 XDS 調(diào)試探針在所有具有嵌入式跟蹤緩沖器 (ETB) 的 ARM 和 DSP 處理器中均支持內(nèi)核和系統(tǒng)跟蹤。對(duì)于引腳上的跟蹤，需要 XDS560v2 PRO TRACE。

XDS560v2 通過 MIPI HSPT 60 引腳連接器（帶有多個(gè)用于 TI 14 引腳、TI 20 引腳和 ARM 20 引腳的適配器）連接到目標(biāo)板，并通過 USB2.0 高速 (480Mbps) (...)

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調(diào)試探針

TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系統(tǒng)跟蹤 USB 和以太網(wǎng)

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 處理器調(diào)試探針（仿真器）的第一種型號(hào)。XDS560v2 是 XDS 系列調(diào)試探針中性能最高的一款，同時(shí)支持傳統(tǒng) JTAG 標(biāo)準(zhǔn) (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存儲(chǔ)器緩沖區(qū)中加入了系統(tǒng)引腳跟蹤。這種外部存儲(chǔ)器緩沖區(qū)適用于指定的 TI 器件，通過捕獲相關(guān)器件級(jí)信息，獲得準(zhǔn)確的總線性能活動(dòng)和吞吐量，并對(duì)內(nèi)核和外設(shè)進(jìn)行電源管理。此外，對(duì)于帶有嵌入式緩沖跟蹤器 (ETB) 的所有 ARM 和 DSP 處理器，所有 XDS (...)

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軟件開發(fā)套件 (SDK)

ANDROIDSDK-SITARA — 適用于 Sitara 微處理器的 Android 開發(fā)套件

雖然起初專為移動(dòng)手持終端而設(shè)計(jì)，Android 操作系統(tǒng)仍允許嵌入式應(yīng)用的設(shè)計(jì)人員輕松為產(chǎn)品增加高級(jí)操作系統(tǒng)。與 Google 聯(lián)合開發(fā)的 Android 是一套可立即實(shí)現(xiàn)集成和生產(chǎn)的全面操作系統(tǒng)。


Android 操作系統(tǒng)的亮點(diǎn)包括：

  • 完整的開放源碼軟件解決方案
  • 基于 Linux
  • 針對(duì)商業(yè)開發(fā)的簡潔許可條款 (Apache)
  • 包含一個(gè)完整的應(yīng)用程序框架
  • 允許通過 Java 輕松集成客戶開發(fā)的應(yīng)用程序
  • 開箱即用的多媒體、圖形和圖形用戶界面
  • 如今已形成龐大的 Android 和應(yīng)用程序開發(fā)人員社區(qū)
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軟件開發(fā)套件 (SDK)

LINUXDVSDK-OMAP3530 — 用于 OMAP3530/3525 數(shù)字媒體處理器的 Linux 數(shù)字視頻軟件開發(fā)套件 (DVSDK)

The Linux Digital Video Software Development Kit (DVSDK) enables OMAP35x system integrators to quickly develop Linux-based multimedia applications that can be easily ported across different devices in the OMAP35x generation, including OMAP3530 and OMAP3525 application processors. The DVSDK combines (...)
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軟件編解碼器

C64XPLUSCODECS — 編解碼器 - 視頻和語音 - 基于 C64x+ 的器件（OMAP35x、C645x、C647x、DM646、DM644x 和 DM643x）

TI 編解碼器免費(fèi)提供，附帶生產(chǎn)許可且現(xiàn)在可供下載。所有編解碼器均經(jīng)過生產(chǎn)環(huán)境測(cè)試，可輕松集成到視頻和語音應(yīng)用中。點(diǎn)擊“獲取軟件”按鈕（上方），獲取經(jīng)過測(cè)試的最新編解碼器版本。該頁面及每個(gè)安裝程序中都包含有數(shù)據(jù)表和發(fā)布說明。

其他信息：

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軟件編解碼器

OMAP35XCODECS — 用于 OMAP35x 的編解碼器 - 軟件和文檔

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into audio, video and voice applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes (...)

支持的產(chǎn)品和硬件

支持的產(chǎn)品和硬件

產(chǎn)品
基于 Arm 的處理器
OMAP3503 — Sitara 處理器：Arm Cortex-A8、LPDDR OMAP3515 — Sitara 處理器：Arm Cortex-A8、3D 圖形、LPDDR OMAP3525 — 應(yīng)用處理器 OMAP3530 — 應(yīng)用處理器
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軟件編程工具

FLASHTOOL — 用于 AM35x、AM37x、DM37x 和 OMAP35x 器件的 FlashTool

Flash Tool is a Windows-based application that can be used to transfer binary images from a host PC to TI Sitara AM35x, AM37x, DM37x and OMAP35x target platforms.


Additional Information:

TI GForge?- Welcome to gforge.ti.com

TI E2E Community

支持的產(chǎn)品和硬件

支持的產(chǎn)品和硬件

產(chǎn)品
基于 Arm 的處理器
AM3505 — Sitara 處理器：Arm Cortex-A8、視頻前端 AM3517 — Sitara 處理器：Arm Cortex-A8、3D 圖形、視頻前端 AM3703 — Sitara 處理器：Arm Cortex-A8、攝像機(jī) AM3715 — Sitara 處理器：Arm Cortex-A8、3D 圖形、攝像機(jī) DM3725 — 數(shù)字媒體處理器 DM3730 — 數(shù)字媒體處理器 OMAP3503 — Sitara 處理器：Arm Cortex-A8、LPDDR OMAP3515 — Sitara 處理器：Arm Cortex-A8、3D 圖形、LPDDR OMAP3525 — 應(yīng)用處理器 OMAP3530 — 應(yīng)用處理器
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仿真模型

OMAP3515/03 CBB IBIS Model (Rev. A)

SPRM320A.ZIP (1575 KB) - IBIS Model
下載
仿真模型

OMAP3515/03 CBB BSDL Model (Rev. C)

SPRM313C.ZIP (11 KB) - BSDL Model
下載
仿真模型

OMAP3515/03 CBC IBIS Model (Rev. A)

SPRM321A.ZIP (1559 KB) - IBIS Model
下載
仿真模型

OMAP3515/03 CBC BSDL MODEL

SPRM473.ZIP (10 KB) - BSDL Model
下載
仿真模型

OMAP3515/03 CUS BSDL Model (Rev. B)

SPRM312B.ZIP (10 KB) - BSDL Model
下載
仿真模型

OMAP3515/03 CUS IBIS Model (Rev. B)

SPRM319B.ZIP (1537 KB) - IBIS Model
下載
計(jì)算工具

POWEREST — 功耗估算工具 (PET)

功耗估算工具 (PET) 讓用戶能夠深入了解部分 TI 處理器的功耗。用戶可以使用此工具選擇多種應(yīng)用方案，了解功耗并了解如何應(yīng)用高級(jí)節(jié)能技術(shù)進(jìn)一步降低整體功耗。
適用于 AM57x 和 AM437x 處理器的 PET：

這個(gè)可下載的電子表格是一種機(jī)制，用戶可以通過該機(jī)制輸入應(yīng)用所需的器件參數(shù)。參數(shù)包括 IP 活動(dòng)/負(fù)載、所需的電源狀態(tài)和電源管理用途。可為每個(gè)狀態(tài)設(shè)定多個(gè)運(yùn)行條件及相應(yīng)的時(shí)間段。功耗估算數(shù)據(jù)嵌入在電子表格中，并會(huì)在電子表格中自動(dòng)生成（無需上傳）。

用于 AM57x 的 PET：

AM437x/AMIC120 (...)

View Options
封裝 引腳 CAD 符號(hào)、封裝和 3D 模型
FCCSP (CBB) 515 Ultra Librarian
FCCSP (CUS) 423 Ultra Librarian

訂購和質(zhì)量

包含信息：
  • RoHS
  • REACH
  • 器件標(biāo)識(shí)
  • 引腳鍍層/焊球材料
  • MSL 等級(jí)/回流焊峰值溫度
  • MTBF/時(shí)基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續(xù)可靠性監(jiān)測(cè)
包含信息：
  • 制造廠地點(diǎn)
  • 封裝廠地點(diǎn)

支持和培訓(xùn)

可獲得 TI 工程師技術(shù)支持的 TI E2E? 論壇

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