The 12-bit, 3.6 GSPS ADC12D1800 is the latest advance in TI’s Ultra-High-Speed ADC family and builds upon the features, architecture and functionality of the 10-bit GHz family of ADCs.
The ADC12D1800 provides a flexible LVDS interface which has multiple SPI programmable options to facilitate board design and FPGA/ASIC data capture. The LVDS outputs are compatible with IEEE 1596.3-1996 and supports programmable common mode voltage.
The product is packaged in a leaded or lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of –40°C to +85°C.
To achieve full rated performance for fCLK > 1.6 GHz, write the maximum power settings one time to Register 6h through the serial interface; see Section 5.6.1 for more information.
| 類型 | 標題 | 下載最新的英語版本 | 日期 | |||
|---|---|---|---|---|---|---|
| * | 數據表 | ADC12D1800 12-Bit, Single 3.6 GSPS Ultra High-Speed ADC 數據表 (Rev. Q) | PDF | HTML | 2017年 5月 17日 | ||
| 應用手冊 | AN-2132 Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature (Rev. G) | 2017年 2月 3日 | ||||
| 應用手冊 | Maximizing SFDR Performance in the GSPS ADC: Spur Sources and Methods of Mitigat | 2013年 12月 9日 | ||||
| 應用手冊 | AN-2128 ADC1xD1x00 Pin Compatibility (Rev. C) | 2013年 5月 1日 | ||||
| 用戶指南 | Schematic and Layout Recommendations for the GSPS ADC | 2013年 4月 29日 | ||||
| 應用手冊 | AN-2177 Using the LMH6554 as a ADC Driver (Rev. A) | 2013年 4月 26日 | ||||
| 應用手冊 | From Sample Instant to Data Output: Understanding Latency in the GSPS ADC | 2012年 12月 18日 | ||||
| 產品概述 | ADC12D1x00 12-bit ADC Family: Ultra High-Speed 12-bit ADCs up to 3.6 GSPS | 2012年 5月 16日 | ||||
| 用戶指南 | 12-Bit, Dual 1.6/1.8 GSPS or Single 3.2/3.6 GSPS Ref Bd User Guide | 2012年 1月 25日 |
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| 封裝 | 引腳 | CAD 符號、封裝和 3D 模型 |
|---|---|---|
| PBGA (NXA) | 292 | Ultra Librarian |
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