ZHCABE6A September 2021 – April 2022 PCM3120-Q1 , PCM5120-Q1 , PCM6120-Q1 , TLV320ADC3120 , TLV320ADC5120 , TLV320ADC6120
下面提供了兩個示例，用于說明在 48KHz 的采樣頻率下如何為兩個不同的目標應用配置 AGC。示例 1 適用于噪聲遠低于輸入信號的情況。示例 2 適用于噪聲明顯大于所需信號的情況。
示例 1：當噪聲的振幅明顯小于信號的振幅時，AGC 可以通過將噪聲閾值設置為高于本底噪聲但低于可能的最弱信號來輕松區(qū)分噪聲和信號。當可以進行這種清晰的區(qū)分時，可以使用更高的最大增益，因為增加噪聲的可能性很小。以下值可用于該應用。
# Key: w 9C XX YY ==> write to I2C address 0x98, to register 0xXX, data 0xYY
# # ==> comment delimiter
#
# The following list gives an example sequence of items that must be executed in the time
# between powering the device up and reading data from the device.Note that there are
# other valid sequences depending on which features are used.
#
# See the corresponding EVM user guide for jumper settings and audio connections.
#
# Differential 2-channel : INP1/INM1 - Ch1, INP2/INM2 - Ch2
# FSYNC = 48 kHz (Output Data Sample Rate), BCLK = 11.2896 MHz (BCLK/FSYNC = 256)
################################################################
#
#
# Power up IOVDD and AVDD power supplies
# Wait for 1ms.
#
w 9C 00 00 # Goto Page 0
w 9C 02 81 # Wake-up device by I2C write into P0_R2 using internal AREG
w 9C 02 81 # Exit Sleep mode
d 10 # Wait for 16 ms
w 9c 6C 4C # Enable AGC in DSP_CFG1 and Override AGC parameters with user values
w 9C 3C 01 # Select AGC on Ch. 1 using CH1_CFG0
w 9C 41 01 # Select AGC on Ch. 2 using CH2_CFG0
w 9C 70 E7 # AGC LVL = -36 dB, AGC GAIN = 24 dB
w 9C 00 05 # Goto Page 5
w 9C 7C 7F B5 16 50 # AGC Release Time Alpha
w 9C 00 05 # Goto Page 6
w 9C 08 00 4A E9 B0 # AGC Release Time Beta
w 9C 0C 50 FC 64 5C # AGC Attack Time Alpha
w 9C 10 2F 03 9B A4 # AGC Attack Time Beta
w 9C 18 00 00 02 00 # AGC Attack Debounce
w 9C 1C 00 04 B0 00 # AGC Release Debounce
w 9C 20 FF FF AB 00 # AGC Noise Threshold : -85 dB
w 9C 44 00 04 B0 00 # AGC Noise Debounce
w 9C 3C 00 00 01 00 # AGC Attack Hysteresis
w 9C 34 00 00 03 00 # AGC Release Hysteresis
w 9C 54 00 00 04 00 # AGC Noise Hysteresis : 4 dB
w 9C 78 7F 7F D2 B4 # AGC HPF B0
w 9c 7C 80 80 2D 4C # AGC HPF B1
w 9C 00 06 # Goto Page 6
w 9c 54 7E FF A5 68 # AGC HPF A1
w 9C 00 00 # Goto Page 0
w 9c 07 30 # TDM Mode with 32 Bits/Channel
w 9C 73 C0 # Enable Ch.1 - Ch.2
w 9C 74 C0 # Enable ASI Output channels
w 9c 75 E0 # Power up ADC
示例 2：當噪聲非常高且不易與微弱信號區(qū)分開來時，不建議使用較高的最大增益。必須將噪聲閾值設置為更接近預期的本底噪聲。以下值可用于該應用。
# Key: w 9C XX YY ==> write to I2C address 0x98, to register 0xXX, data 0xYY
# # ==> comment delimiter
#
# The following list gives an example sequence of items that must be executed in the time
# between powering the device up and reading data from the device.Note that there are
# other valid sequences depending on which features are used.
#
# See the corresponding EVM user guide for jumper settings and audio connections.
#
# Differential 2-channel : INP1/INM1 - Ch1, INP2/INM2 - Ch2
# FSYNC = 48 kHz (Output Data Sample Rate), BCLK = 11.2896 MHz (BCLK/FSYNC = 256)
################################################################
#
#
# Power up IOVDD and AVDD power supplies
# Wait for 1ms.
#
w 9C 00 00 # Goto Page 0
w 9C 02 81 # Wake-up device by I2C write into P0_R2 using internal AREG
w 9C 02 81 # Exit Sleep mode
d 10 # Wait for 16 ms
w 9c 6C 4C # Enable AGC in DSP_CFG1 and Override AGC parameters with user values
w 9C 3C 01 # Select AGC on Ch. 1 using CH1_CFG0
w 9C 41 01 # Select AGC on Ch. 2 using CH2_CFG0
w 9C 70 E5 # AGC LVL = -36 dB, AGC GAIN = 18 dB
w 9C 00 05 # Goto Page 5
w 9C 7C 7F B5 16 50 # AGC Release Time Alpha
w 9C 00 05 # Goto Page 6
w 9C 08 00 4A E9 B0 # AGC Release Time Beta
w 9C 0C 50 FC 64 5C # AGC Attack Time Alpha
w 9C 10 2F 03 9B A4 # AGC Attack Time Beta
w 9C 18 00 00 02 00 # AGC Attack Debounce
w 9C 1C 00 04 B0 00 # AGC Release Debounce
w 9C 20 FF FF B0 00 # AGC Noise Threshold : -80 dB
w 9C 44 00 04 B0 00 # AGC Noise Debounce
w 9C 3C 00 00 01 00 # AGC Attack Hysteresis
w 9C 34 00 00 03 00 # AGC Release Hysteresis
w 9C 54 00 00 04 00 # AGC Noise Hysteresis : 4 dB
w 9C 78 7F 7F D2 B4 # AGC HPF B0
w 9C 7C 80 80 2D 4C # AGC HPF B1
w 9C 00 06 # Goto Page 6
w 9C 54 7E FF A5 68 # AGC HPF A1
w 9C 00 00 # Goto Page 0
w 9C 07 30 # TDM Mode with 32 Bits/Channel
w 9C 73 c0 # Enable Ch.1 - Ch.2
w 9C 74 c0 # Enable ASI Output channels
w 9C 75 e0 # Power up ADC