SNLA426 june 2023 DS320PR1601 , DS320PR410 , DS320PR810 , SN75LVPE5412 , SN75LVPE5421
PCIe Gen5 and lower rates use differential AC coupled transmission lines. Polarity inversion is allowed since NRZ data is used. There is on-chip termination that activates after the Rx detect process is asserted on both inputs and outputs to facilitate signal integrity. More importantly, PCIe Gen3 through Gen5 uses link training, allowing both TX and RX link equalization.
Before we get started discussing PCB layout guidelines, let’s start with PCIe overall design considerations. Table 2-1 outlines the loss budget (dB) for PCIe Gen3 through Gen5, while Table 2-2 outlines the PCIe eye opening requirements for Gen3 through Gen5.
| Loss Breakdown | Gen3 (dB) | Gen4 (dB) | Gen5 (dB) |
|---|---|---|---|
| CPU Package | 3.5 | 5 | 9.0 |
| System Board Trace (9-inch trace with high-loss material) | 13 | 14 | 16 |
| CEM Connector | 0.5 | 0.5 | 1.5 |
| 4” Add-In-Card | 6.5 | 8.5 | 9.5 |
| Total System Loss | 23.5 | 28 | 36 |
| Cross Talk Mitigation | Negligible | <2 | 4-5 |
| Temp/Humidity Loss | - | - | 2-3 |
| Eye Opening | Gen3 | Gen4 | Gen5 |
|---|---|---|---|
| Extrapolated Eye Height after EQ | 25 mV | 15 ± 1.5mV | 15 ± 1.5mV |
| Minimum Eye Width after EQ | 0.3UI (37.5ps) | 0.3UI (18.75 ± 0.55ps) | 0.3UI (9.375 ± 0.5ps) |