SNLA426 june 2023 DS320PR1601 , DS320PR410 , DS320PR810 , SN75LVPE5412 , SN75LVPE5421
- 1
- Abstract
- Trademarks
- 1 Introduction
- 2 PCIe Gen3, Gen4, and Gen5 Loss Budget
- 3 Minimum Eye Width
- 4 Cross Talk Mitigation
- 5 Humidity and Temperature Insertion Loss
- 6 Critical Signals
- 7 General High-Speed Signal Routing
- 8 PCB Grain and Fiber Weave Selection
- 9 PCB Material Loss Budget
- 10High-Speed Signal Trace Impedance
- 11High-Speed Signal Trace Length Matching
- 12Differential Trace Routing Guidelines
- 13Differential-Inter-Pair Matching
- 14Intra-pair Length Matching
- 15Trace Bends
- 16Minimum Differential Trace-To-Trace Distance
- 17Serpentine Guidelines
- 18High-Speed Differential Signal Quick Rules
- 19High-Speed Differential Pair Reference Plane
- 20Via Staggering
- 21Via Stubs
- 22Via Pads
- 23Via Discontinuity Mitigation
- 24Back-Drill Stubs
- 25AC Coupling Capacitors Placement
- 26AC Coupling Capacitor Physical Placement
- 27Auxiliary Signal AC Match Termination
- 28Suggested PCB Stack-ups
- 29Summary
- 30References
12 Differential Trace Routing Guidelines
When matching the intra-pair length of the high-speed signals, add serpentine routing to match the lengths as close to the mismatched ends as possible. For more details, see Figure 12-1.
Figure 12-1 Length Matching