1 Introduction

Peripheral Component Interconnect Express (PCIe) was introduced over two decades ago to enable the growing demand for high bandwidth/speed data transfers. Each new generation for PCIe has effectively doubled the rate of transmission. The current generation, PCIe Gen5, transfers data at a rate of 32 GT/s. High speed interfaces such as PCIe introduced many challenges in regards to layout, including but not limited to traces, vias, reference planes, dielectrics, and so on. All of the factors mentioned previously have significant impacts at high data rates; thus, adhere to the following layout practices to overcome PCIe Gen5 layout challenges.