SLVUC26A March 2021 – April 2021 LM53602-Q1 , LM53603-Q1 , LP8733-Q1 , TDA3MA , TDA3MV , TPS22965-Q1 , TPS54116-Q1 , TPS61240-Q1

5 OTP Memory Configuration, Static Platform Settings

Each device has predefined values stored in OTP which control the default configuration of the device. The tables in this section list the OTP-programmed values for each device, distinguished by the OTP_REV. Power-up and power-down sequences are described in the next chapter, Section 6.

Table 5-1 shows device settings for BUCK0 and BUCK1. Maximum allowed slew-rate for BUCKx depends on the output capacitance. Refer to the device data sheets for output capacitance boundary conditions.

Table 5-1 BUCK0 and BUCK1 OTP Settings

	Description	Bit Name	LP873344	Notes
	Buck configuration		1 + 1	2-phase or 1 + 1
	Switching frequency		2 MHz
	Buck force sink		No	Yes / No
	Spread spectrum	EN_SPREAD_SPEC	No	Yes / No
BUCK0	Output voltage	BUCK0_VSET	1.06 V
	Enable, EN-pin or I²C register	BUCK0_EN_PIN_CTRL, BUCK0_EN	EN	EN or I²C
	Force PWM	BUCK0_FPWM	No	Yes / No
	Peak current limit	BUCK0_ILIM	4 A
	Slew rate	BUCK0_SLEW_RATE	10 mV/μs
BUCK1	Output voltage	BUCK1_VSET	1.06 V
	Enable, EN-pin or I²C register	BUCK1_EN_PIN_CTRL, BUCK1_EN	EN	EN or I²C
	Force PWM	BUCK1_FPWM	No	Yes / No
	Peak current limit	BUCK1_ILIM	4 A
	Slew rate	BUCK1_SLEW_RATE	10 mV/μs

Table 5-2 lists the device settings for LDO0 and LDO1.

Table 5-2 LDO0 and LDO1 OTP Settings

	Description	Bit Name	LP873344	Notes
LDO0	Output voltage	LDO0_VSET	1.8 V
LDO0	Enable, EN-pin or I²C register	LDO0_EN_PIN_CTRL, LDO0_EN	EN	EN or I²C
LDO1	Output voltage	LDO1 _VSET	1.8 V
LDO1	Enable, EN-pin or I²C register	LDO1_EN_PIN_CTRL, LDO1_EN	EN	EN or I²C

Table 5-3 lists the device settings for GPIOs.

Table 5-3 EN, CLKIN and GPIO Pin Settings

	Description	Bit Name	LP873344	Notes
EN pin	EN pin pulldown resistor enable or disable	EN_PD	Enabled	Enabled / disabled
CLKIN pin	CLKIN or GPO2 mode selection	CLKIN_PIN_SEL	GPO2
	CLKIN pin pulldown resistor enable or disable (applicable for both CLKIN and GPO2 modes)	CLKIN_PD	Disabled	Enabled / disabled
	Frequency of external clock when connected to CLKIN	EXT_CLK_FREQ	2 MHz
	Enable for the internal PLL. When PLL disabled, internal RC OSC is used	EN_PLL	Disabled	Enabled / disabled
GPO	GPO output type	GPO_OD	PP	PP / OD
	Enable, EN-pin or I²C register	GPO_EN_PIN_CTRL, GPO_EN	EN
	Control for GPO	GPO_EN	High	Low / High
GPO2	GPO2 output type	GPO2_OD	OD	PP / OD
	Enable, EN-pin or I²C register	GPO2_EN_PIN_CTRL	EN	EN or I²C
	Control for GPO2	GPO2_EN	High	Low / High

Table 5-4 shows device settings for PGOOD.

Table 5-4 PGOOD OTP Settings

	Description	Bit Name	LP873344	Notes
Signals monitored by PGOOD	BUCK0 output voltage	EN_PGOOD_BUCK0	Yes	Yes / No
	BUCK1 output voltage	EN_PGOOD_BUCK1	Yes	Yes / No
	LDO0 output voltage	EN_PGOOD_LDO0	Yes	Yes / No
	LDO1 output voltage	EN_PGOOD_LDO1	Yes	Yes / No
	Thermal warning	EN_PGOOD_TWARN	Yes	Yes / No
PGOOD mode selections	PGOOD thresholds for BUCK0, BUCK1	PGOOD_WINDOW_BUCK	Window	Undervoltage / Window (undervoltage and overvoltage)
	PGOOD thresholds for LDO0, LDO1	PGOOD_WINDOW_LDO	Window	Undervoltage / Window (undervoltage and overvoltage)
	PGOOD operating mode	PGOOD_MODE	Unvalid	UNUSUAL / UNVALID
	PGOOD signal mode	PG_FAULT_GATES_PGOOD	Status	Status / Latched until fault source read
	PGOOD output mode	PGOOD_OD	OD	OD / PP
	PGOOD polarity	PGOOD_POL	Active high	Active (power valid) high / low

Table 5-5 lists the device settings for thermal warning. Also refer to Table 5-4 for PGOOD and Table 5-7 for interrupts.

Table 5-5 Protections OTP Settings

	Description	Bit Name	LP873344	Notes
Protections	Thermal warning level	TDIE_WARN_LEVEL	137°C	125°C or 137°C
Protections	Input overvoltage protection	(Hidden from customer, always enabled)	Enabled	Enabled / disabled

Table 5-6 shows device settings for I²C and OTP revision ID values.

Table 5-6 Device Identification and I²C Settings

	Description	Bit Name	LP873344	Notes
I²C address			0x60
I2C speed default	Set Hs-mode I²C by default		No	Yes / No
DEVICE_ID	Device specific ID code	DEVICE_ID	0x0
OTP_ID	Identification code for OTP version	OTP_ID	0x44

Table 5-7 lists device settings for interrupts. When interrupt from an event is unmasked, an interrupt is generated to nINT pin.

Table 5-7 Interrupt Mask Settings

	Interrupt event	Bit Name	LP873344	Notes
General	PGOOD pin changing active to inactive	PGOOD_INT_MASK	Masked	Masked / Unmasked
	Sync clock appears or disappears	SYNC_CLK_MASK	Masked	Masked / Unmasked
	Thermal warning	TDIE_WRN_MASK	Unmasked	Masked / Unmasked
	Load measurement ready	I_MEAS_MASK	Unmasked	Masked / Unmasked
	Register reset	RESET_REG_MASK	Masked	Masked / Unmasked
BUCK0	Buck0 PGood active	BUCK0_PGR_MASK	Masked	Masked / Unmasked
	Buck0 PGood inactive	BUCK0_PGF_MASK	Masked	Masked / Unmasked
	Buck0 current limit	BUCK0_ILIM_MASK	Unmasked	Masked / Unmasked
BUCK1	Buck1 PGood active	BUCK1_PGR_MASK	Masked	Masked / Unmasked
	Buck1 PGood inactive	BUCK1_PGF_MASK	Masked	Masked / Unmasked
	Buck1 current limit	BUCK1_ILIM_MASK	Unmasked	Masked / Unmasked
LDO0	LDO0 PGood active	LDO0_PGR_MASK	Masked	Masked / Unmasked
	LDO0 PGood inactive	LDO0_PGF_MASK	Masked	Masked / Unmasked
	LDO0 current limit	LDO0_ILIM_MASK	Unmasked	Masked / Unmasked
LDO1	LDO1 PGood active	LDO1_PGR_MASK	Masked	Masked / Unmasked
	LDO1 PGood inactive	LDO1_PGF_MASK	Masked	Masked / Unmasked
	LDO1 current limit	LDO1_ILIM_MASK	Unmasked	Masked / Unmasked