SLVK182 December 2024 DRV8351-SEP
| Parameter | Test Conditions | VCC | TA = -55°C to +125°C | Unit | Test Name | ||
|---|---|---|---|---|---|---|---|
| MIN | TYP | MAX | |||||
| IGVDD | GVDD standby mode current | INHx = INLX = 0; VBSTx = VGVDD | 400 | 800 | 1500 | μA | IGVDD_STANDBY |
| IGVDD | GVDD active mode current | INHx = INLX = Switching at 20kHz; VBSTx = VGVDD; NO FETs connected | 400 | 825 | 1500 | μA | IGVDD_ACTIVE |
| ILBSx | Bootstrap pin leakage current | VBSTx = VSHx = 85V; VGVDD = 0V | 2 | 7 | 13 | μA | IL_BSX |
| ILBS_TRAN | Bootstrap pin active mode transient leakage current | INHx = Switching at 20kHz | 30 | 105 | 220 | μA | IL_BSX_TRAN |
| ILBS_DC | Bootstrap pin active mode leakage static current | INHx = High | 30 | 85 | 150 | μA | IL_BSX_ACT |
| ILSHx | High-side source pin leakage current | INHx = INLX = 0; VBSTx - VSHx = 12V; VSHx = 0 to 85V | 30 | 55 | 90 | μA | IL_SHX_TRAN |
| VIL | Input logic low voltage | INLx, INHx pins | 0.8 | V | VIL_INHX | ||
| IIL | INHx, MODE Input logic low current | VPIN (Pin Voltage) = 0V | -1 | 0 | 1 | μA | IIL_INHX |
| IIH | INHx, MODE Input logic high current | VPIN (Pin Voltage) = 5V; | 5 | 20 | 30 | μA | IIH_INHX |
| RPD_INHx | INHx Input pulldown resistance | To GND | 120 | 200 | 280 | kΩ | RPD_INHX |
| VGHx_LO | High-side gate drive low level voltage | IGLx = -100mA; VGVDD = 12V; No FETs connected | 0 | 0.15 | 0.35 | V | VGHX_LO |
| VGHx_HI | High-side gate drive high level voltage (VBSTx - VGHx) | IGHx = 100mA; VGVDD = 12V; No FETs connected | 0.3 | 0.6 | 1.2 | V | VGHX_HI |
| VGLx_LO | Low-side gate drive low level voltage | IGLx = -100mA; VGVDD = 12V; No FETs connected | 0 | 0.15 | 0.35 | V | VGLX_LO |
| VGLx_HI | Low-side gate drive high level voltage (VGVDD - VGHx) | IGHx = 100mA; VGVDD = 12V; No FETs connected | 0.3 | 0.6 | 1.2 | V | VGLX_HI |
| IDRIVEP_HS | High-side peak source gate current | GHx-SHx = 12V | 400 | 750 | 1200 | mA | IDRIVE_HSX_SOURCE |
| IDRIVEN_HS | High-side peak sink gate current | GHx-SHx = 0V | 850 | 1500 | 2100 | mA | IDRIVE_HSX_SINK |
| IDRIVEP_LS | Low-side peak source gate current | GLx = 12V | 400 | 750 | 1200 | mA | IDRIVE_LSX_SOURCE |
| IDRIVEN_LS | Low-side peak sink gate current | GLx = 0V | 850 | 1500 | 2100 | mA | IDRIVE_LSX_SINK |
| tPD | Input to output propagation delay | INHx, INLx to GHx, GLx; VGVDD = VBSTx - VSHx > 8V; SHx = 0V, No load on GHx and GLx | 70 | 125 | 180 | ns | TPD_GLX_GT8 TPD_GHX_GT8 |
| tPD_match | Matching propagation delay per phase | GHx turning OFF to GLx turning ON, GLx turning OFF to GHx turning ON; VGVDD = VBSTx - VSHx > 8V; SHx = 0V, No load on GHx and GLx | -30 | ±4 | 30 | ns | TPD_MATCH_GT8_LSX TPD_MATCH_GT8_HSX |
| tPD_match | Matching propagation delay phase to phase | GHx/GLx turning ON to GHy/GLy turning ON, GHx/GLx turning OFF to GHy/GLy turning OFF; VGVDD = VBSTx - VSHx > 8V; SHx = 0V, No load on GHx and GLx | -30 | ±4 | 30 | ns | TPD_MATCH_PP_GT8_LS TPD_MATCH_PP_GT8_HS |
| tR_GLx | GLx rise time (10% to 90%) | CLOAD = 1000 pF; VGVDD = VBSTx - VSHx > 8V; SHx = 0V | 10 | 24 | 50 | ns | TRISE_GLX_GT8 |
| tR_GHx | GHx rise time (10% to 90%) | CLOAD = 1000pF; VGVDD = VBSTx - VSHx > 8V; SHx = 0V | 10 | 24 | 50 | ns | TRISE_GHX_GT8 |
| tF_GLx | GLx fall time (90% to 10%) | CLOAD = 1000pF; VGVDD = VBSTx - VSHx > 8V; SHx = 0V | 5 | 12 | 30 | ns | TFALL_GLX_GT8 |
| tF_GHx | GHx fall time (90% to 10%) | CLOAD = 1000pF; VGVDD = VBSTx - VSHx > 8V; SHx = 0V | 5 | 12 | 30 | ns | TFALL_GHX_GT8 |
| tDEAD | Gate drive dead time | DT pin connected to GND | 150 | 215 | 280 | ns | TDEAD_GND_CHX |
| VBOOTD | Bootstrap diode forward voltage | IBOOT = 100μA | 0.45 | 0.7 | 0.85 | V | VBSTD_FW100UA |
| VBOOTD | Bootstrap diode forward voltage | IBOOT = 100mA | 2 | 2.3 | 3.1 | V | VBSTD_FW100MA |
| VGVDDUV | Gate Driver Supply undervoltage lockout (GVDDUV) | Supply rising | 4.45 | 4.6 | 4.7 | V | VGVDD_UV_RISE |
| tGVDDUV | Gate Driver Supply undervoltage deglitch time | 5 | 10 | 13 | μs | TGVDD_UV_DG | |
| tBSTUV | Bootstrap undervoltage deglitch time | 6 | 10 | 22 | μs | TBST_UV_DG | |
| RBOOTD | Bootstrap dynamic resistance (ΔVBOOTD/ΔIBOOT) | IBOOT = 100mA and 80mA | 11 | 15 | 25 | ? | RBSTD_DYN |