5 Impacts and Opportunities of PCB Parasitic Impedance

PCB parasitic impedance increases the effective ballast resistance. In designs with a large value discrete ballast resistor (such as greater than 50 m?), Equation 10 and Equation 6 provides good approximations of the load current and voltage. For small values of ballast resistance (such as less than 50 m?), the parasitic PCB impedance can impact the final current sharing analysis. To enable high performance use cases, R_B can be optimized by reviewing the PCB parasitic impedance and reducing the discrete ballast resistance for each LDO accordingly. A reduction of R_B will increase the current sharing mismatch between each LDO Equation 10 but will increase the load voltage Equation 6 which is usually a desired result.

The interaction of the ballast resistance and PCB impedance is shown in Figure 5-1 assuming a minimum 5 m? ballast is needed. Here, we will limit the discussion to two parallel LDO's although we can extend this to any number of parallel LDO's. The PCB impedance is lumped into one equivalent resistor from each LDO to the load and also between the LDOs. Figure 5-1 then provides the four possible use cases of discrete ballast resistance and PCB impedance. Figure 5-1 (a) and Figure 5-1 (b) show insufficient ballast resistance between the LDOs or between the LDO and the load, which is incorrect and could lead to a current fault condition. Figure 5-1 (c) will current share but the load voltage specification may not be met due to the larger 20 m-ohm impedances. Figure 5-1 (d) is an example where the ballast resistance and PCB impedance has been optimized.

Thus, from Figure 5-1 (a) and (b) there are two sets of PCB impedance which must be reviewed in a system and are illustrated in Figure 5-2 for two parallel LDO's. From Figure 5-2a, R_F1 and R_F2 are the parasitic impedances from the output of each ballast resistor to the load, while R_R1 and R_R2 is the parasitic impedance from the load to the return pin of each LDO. From Figure 5-2b, R_F1-2 is the parasitic impedance between the output side of the ballast resistors used for LDOs 1 and 2 and R_R1-2 is the parasitic impedance between the LDO 1 and 2 return pins. Note that R_F1-2≠ R_F1 + R_F2 and R_R1-2≠ R_R1 + R_R2.

The parasitic impedances R_F1, R_F2, R_R1, R_R2, R_F1-2, and R_R1-2 can be simulated using a post route simulator, such as Altium PDN analysis. Note that when evaluating the parasitic return impedance, thermal pads should not be included in the post route simulation as the point of return for the simulated load. Thermal pads provide a low thermal resistance to dissipate heat, however they do not provide low electrical resistance from the die to ground. Thus, the simulation should be performed back to the ground pin of the LDO.

Upon review of Figure 5-2a, we wish to identify the minimum discrete ballast resistance R_Bn’ necessary to meet Equation 9 by accounting for R_Fn and R_Rn.

Upon review of Figure 5-2b, we wish to identify the minimum discrete ballast resistance R_B’ necessary to meet Equation 9 while accounting for R_F1-2 and R_R1-2.

The new, optimized ballast resistor R_{B_OPT} chosen to account for the parasitic PCB impedance is the maximum value of R_Bn’ and R_B’ as shown in Equation 16. I_OUTn and V_LOAD can be modified as shown in Equation 17 and Equation 18, respectively. If both R_Bn’ and R_B’ provide negative values, then the PCB impedance is higher than the necessary ballast resistance for the desired worst-case current sharing. Thus, a discrete ballast resistor can be removed from the design as the parasitic impedances provide sufficient ballast resistance.

If the voltage at the load must be increased, the PCB impedances can be reduced and / or V_OUTn can be increased to achieve a higher V_LOAD.