Three parallel TPS7A57 LDO's were configured for 0.75 VDC output voltage, supplying a combined 13.2 A load current, with a maximum current imbalance of 1 A (). The TPS7A57 reference voltage is generated using a precision current source and an external resistor see reference [2]. Thus, from Section 3.1 we tie the individual reference voltage pins together to reduce the current sharing imbalance among the three LDO's. The remaining error voltage is a function of the line regulation, load regulation and offset voltage variation. Per the TPS7A57 data sheet, the line regulation is 10 nV/V, the load regulation is 175 μV/A and the offset voltage is ± 2 mV. The offset voltage dominates the total error voltage so we will set V_E = ± 2 mV in the analysis. From Equation 9, R_B = 4 m?. From Section 3, the highest load current for one LDO is when V_E is positive for one and negative for the rest. From Equation 10 we conclude I_OUT1 = 5.07 A and I_OUT2 = I_OUT3 = 4.07 A. We can determine the lowest load for an LDO by assuming one LDO has -V_E while the others have +V_E. From Equation 10 we conclude I_OUT1 = 3.73 A and I_OUT2 = I_OUT3 = 4.73 A.

The parallel LDO’s were implemented onto a PCB and a post route simulation was performed (Figure 6-2). The simulation assumed an ideal V_OUT = 0.75 V and R_B = 2.5 m? for each converter. The simulation results demonstrate the impact of PCB impedance mismatch from each LDO output to the load on the current sharing. Measurements versus simulation data in this configuration show strong correlation (Table 6-1) with the difference due to the slight variation of V_OUT and R_B in the fabricated design compared to the ideal values used in the simulation.