3 Sharing the Audio Bus

PCM6xx0 devices send the digitized audio data through a Time Division Multiplexed (TDM) audio bus. A set of channel transfers starts at the rising edge of FSYNC with the first slot of data (slot 0), followed by the remaining data slots in increasing order (slot1, slot2, and so forth). A slot contains the converted data from an ADC channel. Each slot transmits a bit on the rising or falling edge of BCLK, starting with the most significant bit first. Figure 3 shows an example for TDM bus operation with eight slots when TX_OFFSET is set to 0. In this figure, FSYNC is the frame sync signal from the host processor, BCLK is the bit clock signal from the host processor, and SDOUT is the bus from the PCM6xx0 devices. PCM6xx0 supports up to 64 slots in the SDOUT output.

Figure 3. TDM Mode Standard Protocol Timing (TX_OFFSET = 0)

For proper operation of the audio bus in TDM mode, the number of bit clocks per frame must be greater than or equal to the number of active output channels times the programmed word length of the output channel data, as shown in Equation 1. For the example shown in Figure 1 with four devices, each with four channels, at a 48-KHz sampling rate and 32-bit word length, BCLK ≥ 4 × 4 × 48 000 × 32 = 24.576 MHz. Since the maximum supported BCLK is 25 MHz, the maximum number of devices is dependent on the number of channels used, sample rate, and word length that maintains a bit clock (BCLK) under 25 MHz.

The PCM6xx0 supports two methods of wiring several devices together: Shared TDM or Daisy Chain TDM. The following two sections detail the registers that need to be programmed to configure the PCM6xx0 devices to share the TDM bus in these methods.