ZHCSJE0 September 2018 UCD90320U
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 說明 （續）
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4
Device Functional Modes
- 8.4.1 Rail Monitoring Configuration
- 8.4.2 GPI Configuration
- 8.4.3 Rail Sequence Configuration
- 8.4.4 Fault Responses Configuration
- 8.4.5 GPO Configuration
- 8.4.6 Margining Configuration
- 8.4.7 Pin Selected Rail States Configuration
- 8.4.8 Watchdog Timer
- 8.4.9 System Reset Function
- 8.4.10 Cascading Multiple Devices
- 8.4.11 Rail Monitoring
- 8.4.12 Status Monitoring
- 8.4.13 Data and Error Logging to EEPROM Memory
- 8.4.14 Black Box First Fault Logging
- 8.4.15 PMBus Address Selection
- 8.4.16 ADC Reference
- 8.4.17 Device Reset
- 8.4.18 Brownout
- 8.4.19 Internal Fault Management
- 8.4.20 Single Event Upset
- 8.5 Device Configuration and Programming
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
6 Pin Configuration and Functions
ZWS Package
169-Pin BGA
Top View
Pin Functions
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| ANALOG MONITOR PINS(1) | |||
| AMON1 | E2 | I | Analog input monitor pin |
| AMON2 | E1 | I | Analog input monitor pin |
| AMON3 | F2 | I | Analog input monitor pin |
| AMON4 | F1 | I | Analog input monitor pin |
| AMON5 | B3 | I | Analog input monitor pin |
| AMON6 | A3 | I | Analog input monitor pin |
| AMON7 | B4 | I | Analog input monitor pin |
| AMON8 | A4 | I | Analog input monitor pin |
| AMON9 | B5 | I | Analog input monitor pin |
| AMON10 | A5 | I | Analog input monitor pin |
| AMON11 | B6 | I | Analog input monitor pin |
| AMON12 | A6 | I | Analog input monitor pin |
| AMON13 | C1 | I | Analog input monitor pin |
| AMON14 | C2 | I | Analog input monitor pin |
| AMON15 | B1 | I | Analog input monitor pin |
| AMON16 | B2 | I | Analog input monitor pin |
| AMON17 | G2 | I | Analog input monitor pin |
| AMON18 | G1 | I | Analog input monitor pin |
| AMON19 | H1 | I | Analog input monitor pin |
| AMON20 | H2 | I | Analog input monitor pin |
| AMON21 | B7 | I | Analog input monitor pin |
| AMON22 | A7 | I | Analog input monitor pin |
| AMON23 | B8 | I | Analog input monitor pin |
| AMON24 | A8 | I | Analog input monitor pin |
| ENABLE PINS | |||
| EN1(GPIO) | M9 | I/O | Digital output, rail enable signal or GPIO(2) |
| EN2(GPIO) | N9 | I/O | Digital output, rail enable signal or GPIO |
| EN3(GPIO) | L10 | I/O | Digital output, rail enable signal or GPIO |
| EN4(GPIO) | K10 | I/O | Digital output, rail enable signal or GPIO |
| EN5(GPIO) | L9 | I/O | Digital output, rail enable signal or GPIO |
| EN6(GPIO) | K9 | I/O | Digital output, rail enable signal or GPIO |
| EN7(GPIO) | N8 | I/O | Digital output, rail enable signal or GPIO |
| EN8(GPIO) | M8 | I/O | Digital output, rail enable signal or GPIO |
| EN9(GPIO) | L8 | I/O | Digital output, rail enable signal or GPIO |
| EN10(GPIO) | K8 | I/O | Digital output, rail enable signal or GPIO |
| EN11(GPIO) | N7 | I/O | Digital output, rail enable signal or GPIO |
| EN12(GPIO) | M7 | I/O | Digital output, rail enable signal or GPIO |
| EN13(GPIO) | K7 | I/O | Digital output, rail enable signal or GPIO |
| EN14(GPIO) | L7 | I/O | Digital output, rail enable signal or GPIO |
| EN15(GPIO) | N4 | I/O | Digital output, rail enable signal or GPIO |
| EN16(GPIO) | N3 | I/O | Digital output, rail enable signal or GPIO |
| EN17(GPIO) | K3 | I/O | Digital output, rail enable signal or GPIO |
| EN18(GPIO) | K4 | I/O | Digital output, rail enable signal or GPIO |
| EN19(GPIO) | J4 | I/O | Digital output, rail enable signal or GPIO |
| EN20(GPIO) | J2 | I/O | Digital output, rail enable signal or GPIO |
| EN21(GPIO) | J3 | I/O | Digital output, rail enable signal or GPIO |
| EN22(GPIO) | H4 | I/O | Digital output, rail enable signal or GPIO |
| EN23(GPIO) | H3 | I/O | Digital output, rail enable signal or GPIO |
| EN24(GPIO) | G4 | I/O | Digital output, rail enable signal or GPIO |
| EN25(GPIO) | F13 | I/O | Digital output, rail enable signal or GPIO |
| EN26(GPIO) | F12 | I/O | Digital output, rail enable signal or GPIO |
| EN27(GPIO) | G11 | I/O | Digital output, rail enable signal or GPIO |
| EN28(GPIO) | H10 | I/O | Digital output, rail enable signal or GPIO |
| EN29(GPIO) | H13 | I/O | Digital output, rail enable signal or GPIO |
| EN30(GPIO) | H12 | I/O | Digital output, rail enable signal or GPIO |
| EN31(GPIO) | H11 | I/O | Digital output, rail enable signal or GPIO |
| EN32(GPIO) | L13 | I/O | Digital output, rail enable signal or GPIO |
| CLOSED-LOOP MARGIN PINS | |||
| MAR1(GPIO) | J13 | I/O | Closed-loop margin PWM output or General GPIO |
| MAR2(GPIO) | L5 | I/O | Closed-loop margin PWM output or General GPIO |
| MAR3(GPIO) | D8 | I/O | Closed-loop margin PWM output or General GPIO |
| MAR4(GPIO) | K6 | I/O | Closed-loop margin PWM output or General GPIO |
| MAR5(GPIO) | D4 | I/O | Closed-loop margin PWM output or General GPIO |
| MAR6(GPIO) | E4 | I/O | Closed-loop margin PWM output or General GPIO |
| MAR7(GPIO) | F5 | I/O | Closed-loop margin PWM output or General GPIO |
| MAR8(GPIO) | N5 | I/O | Closed-loop margin PWM output or General GPIO |
| MAR9(GPIO) | N6 | I/O | Closed-loop margin PWM output or General GPIO |
| MAR10(GPIO) | K5 | I/O | Closed-loop margin PWM output or General GPIO |
| MAR11(GPIO) | M6 | I/O | Closed-loop margin PWM output or General GPIO |
| MAR12(GPIO) | L6 | I/O | Closed-loop margin PWM output or General GPIO |
| MAR13(GPIO) | D11 | I/O | Closed-loop margin PWM output or General GPIO |
| MAR14(GPIO) | C12 | I/O | Closed-loop margin PWM output or General GPIO |
| MAR15(GPIO) | A13 | I/O | Closed-loop margin PWM output or General GPIO |
| MAR16(GPIO) | B13 | I/O | Closed-loop margin PWM output or General GPIO |
| MAR17(GPIO) | D12 | I/O | Closed-loop margin PWM output or General GPIO |
| MAR18(GPIO) | C13 | I/O | Closed-loop margin PWM output or General GPIO |
| MAR19(GPIO) | E12 | I/O | Closed-loop margin PWM output or General GPIO |
| MAR20(GPIO) | E13 | I/O | Closed-loop margin PWM output or General GPIO |
| MAR21(GPIO) | M13 | I/O | Closed-loop margin PWM output or General GPIO |
| MAR22(GPIO) | L12 | I/O | Closed-loop margin PWM output or General GPIO |
| MAR23(GPIO) | M5 | I/O | Closed-loop margin PWM output or General GPIO |
| MAR24(GPIO) | J12 | I/O | Closed-loop margin PWM output or General GPIO |
| GPIO AND CASCADING PINS | |||
| DMON1(GPIO) | F4 | I/O | Digital input monitor pin or GPIO |
| DMON2(GPIO) | F3 | I/O | Digital input monitor pin or GPIO |
| DMON3(GPIO) | G3 | I/O | Digital input monitor pin or GPIO |
| DMON4(GPIO) | D10 | I/O | Digital input monitor pin or GPIO |
| DMON5(GPIO) | L11 | I/O | Digital input monitor pin or GPIO |
| DMON6(GPIO) | N12 | I/O | Digital input monitor pin or GPIO |
| DMON7(GPIO) | N11 | I/O | Digital input monitor pin or GPIO |
| DMON8(GPIO) | M11 | I/O | Digital input monitor pin or GPIO |
| GPIO | |||
| GPIO1 | B11 | I/O | GPIO |
| GPIO2 | B12 | I/O | GPIO |
| GPIO3 | C11 | I/O | GPIO |
| GPIO4 | A12 | I/O | GPIO |
| SYNC_CLK | K2 | I/O | Synchronization clock I/O for multiple chip cascading |
| LOGIC GPO PINS | |||
| LGPO1(GPIO) | C9 | I/O | Logic GPO or GPIO |
| LGPO2(GPIO) | B9 | I/O | Logic GPO or GPIO |
| LGPO3(GPIO) | A9 | I/O | Logic GPO or GPIO |
| LGPO4(GPIO) | C8 | I/O | Logic GPO or GPIO |
| LGPO5(GPIO) | D5 | I/O | Logic GPO or GPIO |
| LGPO6(GPIO) | C5 | I/O | Logic GPO or GPIO |
| LGPO7(GPIO) | C6 | I/O | Logic GPO or GPIO |
| LGPO8(GPIO) | C4 | I/O | Logic GPO or GPIO |
| LGPO9(GPIO) | L3 | I/O | Logic GPO or GPIO |
| LGPO10(GPIO) | M1 | I/O | Logic GPO or GPIO |
| LGPO11(GPIO) | M2 | I/O | Logic GPO or GPIO |
| LGPO12(GPIO) | M3 | I/O | Logic GPO or GPIO |
| LGPO13(GPIO) | L4 | I/O | Logic GPO or GPIO |
| LGPO14(GPIO) | N1 | I/O | Logic GPO or GPIO |
| LGPO15(GPIO) | M4 | I/O | Logic GPO or GPIO |
| LGPO16(GPIO) | N2 | I/O | Logic GPO or GPIO |
| PMBus COMM INTERFACE | |||
| PMBUS_CLK | E10 | I | PMBus clock (must pull up to V33D) |
| PMBUS_DATA | D13 | I/O | PMBus data (must pull up to V33D) |
| PMBALERT | F11 | O | PMBus alert, active-low, open-drain output (must pull up to V33D) |
| PMBUS_CNTRL | E11 | I | PMBus control pin |
| PMBUS_ADDR0 | L2 | I | PMBus digital address input. Bit 0 |
| PMBUS_ADDR1 | L1 | I | PMBus digital address input. Bit 1 |
| PMBUS_ADDR2 | K1 | I | PMBus digital address input. Bit 2 |
| JTAG | |||
| JTAG_TMS | A10 | I | Test mode select with internal pull-up |
| JTAG_TCK | C10 | I | Test clock with internal pull-up |
| JTAG_TDO | A11 | O | Test data out with internal pull-up |
| JTAG_TDI | B10 | I | Test data in with internal pull-up |
| INPUT POWER, GROUND, AND EXTERNAL REFERENCE PINS | |||
| RESET | G10 | I | Active-low device reset input. Pull up to V33D. |
| V33A | D3 | I | Analog 3.3-V supply. Decouple from V33D to minimize the electrical noise contained on V33D from affecting the analog functions. |
| V33D | D7, E6, E8, E9, F10, J7, J9, J10 | I | Digital 3.3-V supply for I/O and some logic. |
| BPCap | D6, J1, J6, K13 | I | Positive supply for most of the logic function, including the processor core and most peripherals. The voltage on this pin is 1.2 V and is supplied by the on-chip LDO. The BPCap pins should only be connected to each other and an external capacitor as specified in On-Chip Low Drop-Out (LDO) Regulator section of the Electrical Characteristics table. |
| AVSS | C3, E3 | I | Analog ground. These are separated from DVSS to minimize the electrical noise contained on V33D from affecting the analog functions. |
| DVSS | A1, C7, D9, E5, F9, H5, H9, J5, J8, J11, H6, H7, H8, G5, G6, G7, G8, G9, F6, F7, F8, E7 | I | Ground reference for logic and I/O pins. |
| VREFA+ | D2 | I | (Optional) positive node of external reference voltage |
| VREFA- | D1 | I | (Optional) negative node of external reference voltage |
| UNUSED PINS | |||
| UNUSED-NC | A2, G13, M12, N10 | – | Do not connect. Leave floating or isolated. |
| UNUSED-DVSS | G12, K11, M10, N13 | – | Tie to DVSS. |
| UNUSED-V33D | K12 | – | Tie to V33D. |
(1) TI recommends placing a 200-Ω resistor between analog input and monitor pins.
(2) GPIO: GPI, Command GPO, WDI, WDO, system reset (RESET), FAULT pin for multiple chip cascading