ZHCSKG7B June 2019 – February 2024 UCC5390-Q1
PRODUCTION DATA
| PIN | TYPE(1) | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| GND1 | 4 | G | Input ground. All signals on the input side are referenced to this ground. |
| GND2 | 7 | G | Gate-drive common pin. Connect this pin to the IGBT emitter or MOSFET source. UVLO referenced to GND2. |
| IN+ | 2 | I | Noninverting gate-drive voltage-control input. The IN+ pin has a CMOS input threshold. This pin is pulled low internally if left open. Use Function Table to understand the input and output logic of these devices. |
| IN– | 3 | I | Inverting gate-drive voltage control input. The IN– pin has a CMOS input threshold. This pin is pulled high internally if left open. Use Function Table to understand the input and output logic of these devices. |
| OUT | 6 | O | Gate-drive output |
| VCC1 | 1 | P | Input supply voltage. Connect a locally decoupled capacitor to GND1. Use a low-ESR or ESL capacitor located as close to the device as possible. |
| VCC2 | 5 | P | Positive output supply rail. Connect a locally decoupled capacitor to VEE2. Use a low-ESR or ESL capacitor located as close to the device as possible. |
| VEE2 | 8 | G | Negative output supply rail. Connect a locally decoupled capacitor to GND2. Use a low-ESR or ESL capacitor located as close to the device as possible. |