ZHCSQ75C June 2022 – March 2023 UCC28C50-Q1 , UCC28C51-Q1 , UCC28C52-Q1 , UCC28C53-Q1 , UCC28C54-Q1 , UCC28C55-Q1 , UCC28C56H-Q1 , UCC28C56L-Q1 , UCC28C57H-Q1 , UCC28C57L-Q1 , UCC28C58-Q1 , UCC28C59-Q1
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說(shuō)明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Device Functional Modes
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1 Design Requirements
- 9.2.2
Detailed Design Procedure
- 9.2.2.1 Primary-to-Secondary Turns Ratio of the Flyback Transformer (NPS)
- 9.2.2.2 Primary Magnetizing Inductance of the Flyback Transformer (LM)
- 9.2.2.3 Number of Turns of the Flyback Transformer Windings
- 9.2.2.4 Current Sense Resistors (R24, R25) and Current Limiting
- 9.2.2.5 Primary Clamp Circuit (D7, D1, D3, R2, R28) to Limit Voltage Stress
- 9.2.2.6 Primary-Side Current Stress and Input Capacitor Selection
- 9.2.2.7 Secondary-Side Current Stress and Output Capacitor Selection
- 9.2.2.8 VDD Capacitors (C12, C18)
- 9.2.2.9 Gate Drive Network (R14, R16, Q6)
- 9.2.2.10 VREF Capacitor (C18)
- 9.2.2.11 RT/CT Components (R12, C15)
- 9.2.2.12 HV Start-Up Circuitry for VDD (Q1, Q2, D2, D4, D6, D8, R5)
- 9.2.2.13 Desensitization to CS-pin Noise by RC Filtering, Leading-Edge Blanking, and Slope Compensation
- 9.2.2.14 Voltage Feedback Compensation
- 9.2.3 Application Curves
- 9.3 PCB Layout Recommendations
- 9.4 Power Supply Recommendations
- 10Device and Documentation Support
- 11Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- D|8
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購(gòu)信息
8.3.1.7 VDD
VDD is the power input connection for this device. In normal operation, power VDD through a current limiting resistor. The absolute maximum supply voltage is 30 V, extended from 20 V of UCC28C5x-Q1 to facilitate more designs and applications. The 30-V voltage, including any transients that may be present, cannot be exceeded, device damage is likely if otherwise. Hence UCC28C5x devices match the predecessor bipolar devices, which could survive up to 30 V on the input bias pin. But still, no internal clamp is included in the device, the VDD pin must be protected from external sources which could exceed the 30 V level. If containing the start-up and bootstrap supply voltage from the auxiliary winding NA below 30 V under all line and load conditions can not be achieved, use a zener protection diode from VDD to GND. Depending on the impedance and arrangement of the bootstrap supply, this may require adding a resistor, RVDD, in series with the auxiliary winding to limit the current into the zener as shown in Figure 8-1. Insure that over all tolerances and temperatures, the minimum zener voltage is higher than the highest UVLO upper turn-on threshold. To ensure against noise related problems, filter VDD with a ceramic bypass capacitor to GND. The VDD pin must be decoupled as close to the GND pin as possible.
Figure 8-1 VDD ProtectionAlthough nominal VDD operating current is only 1.3 mA, the total supply current is higher, depending on the OUT current. Total VDD current is the sum of quiescent VDD current and the average OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUT current can be calculated from Equation 1.
