国产精品麻豆99久久,狠狠色婷婷狠狠狠亚洲综合,国产女人高潮抽搐喷水嗷嗷叫

ZHCSQ75C June 2022 – March 2023 UCC28C50-Q1 , UCC28C51-Q1 , UCC28C52-Q1 , UCC28C53-Q1 , UCC28C54-Q1 , UCC28C55-Q1 , UCC28C56H-Q1 , UCC28C56L-Q1 , UCC28C57H-Q1 , UCC28C57L-Q1 , UCC28C58-Q1 , UCC28C59-Q1

PRODUCTION DATA

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

D|8
- MSOI002K

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購信息

zhcsq75c_oa

7.5 Electrical Characteristics

V_VDD = 20 V ⁽¹⁾(for UCC28C56H/L-Q1, UCC28C57H/L-Q1 and UCC28C58/9-Q1), V_VDD = 15 V⁽¹⁾ (for the rest), R_RT = 10 kΩ, C_CT = 3.3 nF, C_VDD = 0.1 μF and no load on the outputs, T_J = –40°C to 150°C (unless otherwise noted).

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
REFERENCE
V_VREF	VREF voltage, initial accuracy	I_OUT = 1 mA	4.95	5	5.05	V
	Line regulation	V_VDD = 12 V to 25 V		0.2	20	mV
	Load regulation	1 mA to 20 mA		3	25	mV
	Temperature stability	See ⁽²⁾		0.2	0.4	mV/°C
	Total output variation	See ⁽²⁾	4.82		5.18	V
	VREF noise voltage	10 Hz to 10 kHz, T_J = 25°C, see ⁽²⁾		50		μV
	Long term stability	1000 hours, T_J = 150°C, see ⁽²⁾		5	25	mV
I_VREF	Output short circuit (source current)		30	45	55	mA
OSCILLATOR
f_OSC	Initial accuracy	T_J = 25°C, see ⁽³⁾	50.5	53	55	kHz
f_OSC	Initial accuracy	T_J = Full Range, see ⁽³⁾	50.5		57	kHz
	Voltage stability	12 V ≤ V_VDD ≤ 25 V		0.2%	1%
	Temperature stability	T_J(MIN) to T_J(MAX), see ⁽²⁾		1%	2.5%
	Amplitude	RT/CT pin peak-to-peak voltage		1.9		V
	Discharge current	T_J = 25°C, V_RT/CT = 2 V, see ⁽⁴⁾	7.7	8.4	9	mA
	Discharge current	T_J = Full Range, V_RT/CT = 2 V, see ⁽⁴⁾	7.2	8.4	9.5	mA
ERROR AMPLIFIER
V_FB	Feedback input voltage, initial accuracy	T_J = 25°C, V_COMP = 2.5 V	2.475	2.5	2.525	V
	Feedback input voltage, total variation	T_J = Full Range, V_COMP = 2.5 V	2.45	2.5	2.55	V
I_FB	Input bias current	V_FB = 5 V, (sourcing current)		0.1	2	μA
A_VOL	Open-loop voltage gain	2 V ≤ V_OUT ≤ 4 V	65	90		dB
	Unity gain bandwidth	See ⁽²⁾	1	1.5		MHz
PSRR	Power supply rejection ratio	12 V ≤ V_VDD ≤ 25 V	60			dB
	Output sink current	V_FB = 2.7 V, V_COMP = 1.1 V	2	14		mA
	Output source current	V_FB = 2.3 V, V_COMP = 5 V, (sourcing current)	0.5	1		mA
VOH	High-level COMP voltage	V_FB = 2.7 V, R_COMP = 15 kΩ COMP to GND	V_REF–0.2			V
VOL	Low-level COMP voltage	V_FB = 2.7 V, R_COMP = 15 kΩ COMP to VREF		0.1	1.1	V
CURRENT SENSE
A_CS	Gain	T_J = 25°C, See ⁽⁵⁾	2.85	3	3.15	V/V
A_CS	Gain	T_J = Full Range, See ⁽⁵⁾	2.75	3	3.15	V/V
V_CS	Maximum input signal	V_FB < 2.4 V	0.9	1	1.1	V
PSRR	Power supply rejection ratio	V_VDD = 12 V to 25 V⁽²⁾⁽⁵⁾		70		dB
I_CS	Input bias current (source current)			0.1	2	μA
t_D	CS to output delay			35	70	ns
	COMP to CS offset	V_CS = 0 V		1.15		V
OUTPUT
V_OUT(low)	R_DS(on) pulldown	I_SINK = 200 mA		5.5	15	Ω
V_OUT(high)	R_DS(on) pullup	I_SOURCE = 200 mA		10	25	Ω
t_RISE	Rise tIme	T_J = 25°C, C_OUT = 1 nF		25	50	ns
t_FALL	Fall tIme	T_J = 25°C, C_OUT = 1 nF		20	40	ns
UNDERVOLTAGE LOCKOUT
VDD_ON	Start threshold⁽⁶⁾	UCC28C52-Q1, UCC28C54-Q1	13.5	14.5	15.5	V
		UCC28C53-Q1, UCC28C55-Q1	7.8	8.4	9
		UCC28C50-Q1, UCC28C51-Q1	6.5	7	7.5
		UCC28C56H-Q1, UCC28C57H-Q1	17.6	18.8	20
		UCC28C56L-Q1, UCC28C57L-Q1	17.6	18.8	20
		UCC28C58-Q1, UCC28C59-Q1	14.8	16	17.2
VDD_OFF	Minimum operating voltage ⁽⁶⁾	UCC28C52-Q1, UCC28C54-Q1	8	9	10	V
		UCC28C53-Q1, UCC28C55-Q1	7	7.6	8.2
		UCC28C50-Q1, UCC28C51-Q1	6.1	6.6	7.1
		UCC28C56H-Q1, UCC28C57H-Q1	15	15.5	16
		UCC28C56L-Q1, UCC28C57L-Q1	13.95	14.5	15
		UCC28C58-Q1, UCC28C59-Q1	12	12.5	13
VDD_Hyst	VDD_ON - VDD_OFF⁽⁶⁾	UCC28C52-Q1, UCC28C54-Q1	5.4	5.5		V
		UCC28C53-Q1, UCC28C55-Q1	0.8	0.9
		UCC28C51-Q1, UCC28C50-Q1	0.4	0.5
		UCC28C56H-Q1, UCC28C57H-Q1	2.6	3.3
		UCC28C56L-Q1, UCC28C57L-Q1	3.65	4.3
		UCC28C58-Q1, UCC28C59-Q1	2.8	3.5
PWM
D_MAX	Maximum duty cycle	UCC28C52-Q1, UCC28C53-Q1, UCC28C50-Q1, V_FB < 2.4 V	94%	96%
		UCC28C56H-Q1, UCC28C56L-Q1, UCC28C58-Q1, V_FB < 2.4 V	94%	96%
		UCC28C54-Q1, UCC28C55-Q1, UCC28C51-Q1, V_FB < 2.4 V	47%	48%
		UCC28C57H-Q1, UCC28C57L-Q1, UCC28C59-Q1, V_FB < 2.4 V	47%	48%
D_MIN	Minimum duty cycle	V_FB > 2.6 V			0%
CURRENT SUPPLY
I_START-UP	Start-up current	V_VDD = VDD_ON – 0.5 V		50	75	μA
I_VDD	Operating supply current	V_FB = V_CS = 0 V		1.3	2	mA

(1) Adjust V_VDD above the start threshold before setting at 20 V for UCC28C56H/L-Q1, UCC28C57H/L-Q1 and UCC28C58/9-Q1, and 15.5 V for the rest family.

(2) Ensured by design. Not production tested.

(3) Output frequencies of the UCC28C51-Q1, UCC28C54-Q1, UCC28C55-Q1, UCC28C57H/L-Q1, and the UCC28C59-Q1 are half the oscillator frequency.

(4) Oscillator discharge current is measured with R_RT = 10 kΩ to VREF.

(5) Parameter measured at trip point of latch with V_FB = 0 V. Gain is defined as A_CS = ΔV_COMP / ΔV_CS , 0 V ≤ V_CS ≤ 900 mV.

(6) VDD_ON, VDD_OFF, and V_REF are tracking each other in the same direction, e.g., min VDD_OFF is due to min VDD_ON.