The design of the compensation loop involves selecting the appropriate components so that the required gain, poles, and zeros can be designed to result in a stable system over the entire operating range. There are three distinct portions of the loop: the TL431A-Q1 (or TL431B-Q1), the opto-coupler, and the error amplifier. Each of these stages combines with the power stage to result in a stable robust system.

For good transient response, the bandwidth of the finalized design must be as large as possible. The bandwidth of a CCM flyback, f_BW, is limited to ? of the RHP zero frequency, or approximately 1.77 kHz using Equation 41.

Equation 41.

The gain of the open-loop power stage at f_BW can be calculated using Equation 40 or can be observed on the Bode plot (Figure 9-3) and is equal to –19.55 dB and the phase at f_BW is equal to –58°.

The secondary side portion of the compensation loop begins with establishing the regulated steady state output voltage. To set the regulated output voltage, a TL431A-Q1 (or TL431B-Q1) adjustable precision shunt regulator is ideally suited for use on the secondary side of isolated converters due to its accurate voltage reference and internal op-amp. The resistors used in the divider from the output terminals of the converter to the TL431A-Q1 (or TL431B-Q1) REF pin are selected based upon the desired power consumption. Because the REF input current for the TL431A-Q1 (or TL431B-Q1) is only 2 μA, selecting the resistors for a divider current (I_{FB_REF}) of 1 mA results in minimal error. The top divider resistor (R_FBU) is calculated:

Equation 42.

The TL431A-Q1 (or TL431B-Q1) reference voltage (REF_TL431) has a typical value of 2.495 V. A 9.53-kΩ resistor is chosen for R_FBU. To set the output voltage to 12 V, 2.49 kΩ is used for R_FBB.

Equation 43.

For good phase margin, a compensator zero (f_COMPz) is required and should be placed at 1/10th the desired bandwidth:

Equation 44.

Equation 45.

With this converter, f_COMPz should be set at approximately 177 Hz. A series resistor (R_COMPz) and capacitor (C_COMPz) placed across the TL431A-Q1 (or TL431B-Q1) cathode to REF sets the compensator zero location. Setting C_COMPz to 0.01 μF, R_COMPz is calculated:

Equation 46.

Using a standard value of 88.7 kΩ for R_Z and a 0.01 μF for C_Z results in a zero placed at 179 Hz.

In Figure 9-2, R_TLbias provides cathode current to the TL431A-Q1 (or TL431B-Q1) from the regulated voltage provided from the Zener diode (D_REG). For robust performance, 10 mA is provided to bias the TL431A-Q1 (TL431B-Q1) by way of the 10-V Zener and a 1-kΩ resistor is used for R_TLbias.

The gain of the TL431A-Q1 (or TL431B-Q1) portion of the compensation loop is calculated with Equation 47.

Equation 47.

A compensation pole is required at the frequency of right half plane zero or the ESR zero, whichever is lowest. Based previous the analysis, the right half plane zero (f_RHPz) is located at 7.07 kHz and the ESR zero (f_ESRz) is at 1.68 kHz; therefore, for this design, the compensation pole must be put at 1.68 kHz. The opto-coupler contains a parasitic pole that is difficult to characterize over frequency so the opto-coupler is set up with a pull-down resistor (R_OPTO) equal to 1 kΩ, which moves the parasitic opto-coupler pole further out and beyond the range of interest for this design.

The required compensation pole can be added to the primary side error amplifier using R_COMPp and C_COMPp. Choosing R_COMPp as 10 kΩ, the required value of C_COMPp is determined using Equation 48.

Equation 48.

A 10-nF capacitor is used for C_COMPp setting the compensation pole at 1.59 kHz.

Adding a DC gain to the primary-side error amplifier may be required to obtain the required bandwidth and helps to adjust the loop gain as needed. Using 4.99 kΩ for R_FBG sets the DC gain on the error amplifier to 2. At this point the gain transfer function of the error amplifier stage (G_EA(s)) of the compensation loop can be characterized using Equation 49.

Equation 49.

Using an opto-coupler whose current transfer ratio (CTR) is typically at 100% in the frequency range of interest so that CTR = 1, the transfer function of the opto-coupler stage (G_OPTO(s)) is found using Equation 50.

Equation 50.

The bias resistor (R_LED) to the internal diode of the opto-coupler and the pull-down resistor on the opto emitter (R_OPTO) sets the gain across the isolation boundary. R_OPTO has already been set to 1 kΩ but the value of R_LED has not yet been determined.

The total closed loop gain (G_TOTAL(s)) is the combination of the open-loop power stage (H_o(s)), the opto gain (G_OPTO(s)), the error amplifier gain (G_EA(s)), and the gain of the TL431A-Q1 (or TL431B-Q1) stage (G_TL431(s)), as shown in Equation 51.

Equation 51.

The required value for R_LED can be selected to achieve the desired crossover frequency (f_BW). By setting the total loop gain equal to 1 at the desired crossover frequency and rearranging Equation 51, the optimal value for R_LED can be determined, as shown in Equation 52.

Equation 52.

A 1.3-kΩ resistor suits the requirement for R_LED.

Based on the compensation loop structure, the entire compensation loop transfer function is written as Equation 53.

Equation 53.

The final closed-loop bode plots are show in Figure 9-5 and Figure 9-6. The converter achieves a crossover frequency of approximately 1.8 kHz and has a phase margin of approximately 67°.

TI recommends checking the loop stability across all the corner cases including component tolerances to ensure system stability.

Figure 9-5 Converter Closed-Loop Bode Plot – Gain

Figure 9-6 Converter Closed-Loop Bode Plot – Phase