ZHCSFK9C September 2016 – October 2024 UCC28950-Q1 , UCC28951-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Pin Configuration and Functions
- 5 Specifications
-
6 Detailed Description
- 6.1 Overview
- 6.2 Functional Block Diagram
- 6.3
Feature Description
- 6.3.1 Start-Up Protection Logic
- 6.3.2 Voltage Reference (VREF)
- 6.3.3 Error Amplifier (EA+, EA–, COMP)
- 6.3.4 Soft-Start and Enable (SS/EN)
- 6.3.5 Light-Load Power Saving Features
- 6.3.6 Adaptive Delay, (Delay Between OUTA and OUTB, OUTC and OUTD (DELAB, DELCD, ADEL))
- 6.3.7 Adaptive Delay (Delay Between OUTA and OUTF, OUTB and OUTE (DELEF, ADELEF)
- 6.3.8 Minimum Pulse (TMIN)
- 6.3.9 Burst Mode
- 6.3.10 Switching Frequency Setting
- 6.3.11 Slope Compensation (RSUM)
- 6.3.12 Dynamic SR ON/OFF Control (DCM Mode)
- 6.3.13 Current Sensing (CS)
- 6.3.14 Cycle-by-Cycle Current Limit Current Protection and Hiccup Mode
- 6.3.15 Synchronization (SYNC)
- 6.3.16 Outputs (OUTA, OUTB, OUTC, OUTD, OUTE, OUTF)
- 6.3.17 Supply Voltage (VDD)
- 6.3.18 Ground (GND)
- 6.4 Device Functional Modes
-
7 Application and Implementation
- 7.1 Application Information
- 7.2
Typical Application
- 7.2.1 Design Requirements
- 7.2.2
Detailed Design Procedure
- 7.2.2.1 Power Loss Budget
- 7.2.2.2 Preliminary Transformer Calculations (T1)
- 7.2.2.3 QA, QB, QC, QD FET Selection
- 7.2.2.4 Selecting LS
- 7.2.2.5 Selecting Diodes DB and DC
- 7.2.2.6 Output Inductor Selection (LOUT)
- 7.2.2.7 Output Capacitance (COUT)
- 7.2.2.8 Select FETs QE and QF
- 7.2.2.9 Input Capacitance (CIN)
- 7.2.2.10 Current Sense Network (CT, RCS, R7, DA)
- 7.2.3 Application Curves
- 7.3 Power Supply Recommendations
- 7.4 Layout
- 8 Device and Documentation Support
- 9 Revision History
- 10Mechanical, Packaging, and Orderable Information
4 Pin Configuration and Functions
Figure 4-1 PW Package, 24-Pin TSSOP (Top
View) Pin
Functions
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| ADEL | 14 | I | Dead-time programming for the primary switches over CS voltage range, tABSET and tCDSET. See Section 6.3.6 |
| ADELEF | 13 | I | Delay-time programming between primary side and secondary side switches, tAFSET and tBESET. See Section 6.3.7 |
| COMP | 4 | I/O | Error amplifier output and input to the PWM comparator. See Section 6.3.3 |
| CS | 15 | I | Current sense for cycle-by-cycle overcurrent protection and adaptive delay functions. See Section 6.3.14 |
| DCM | 12 | I | DCM threshold setting. See Section 6.3.12 |
| DELAB | 6 | I | Dead-time delay programming between OUTA and OUTB. See Section 6.3.6 |
| DELCD | 7 | I | Dead-time delay programming between OUTC and OUTD. See Section 6.3.6 |
| DELEF | 8 | I | Delay-time programming between OUTA to OUTF, and OUTB to OUTE. See Section 6.3.7 |
| EA+ | 2 | I | Error amplifier noninverting input. See Section 6.3.3 |
| EA– | 3 | I | Error amplifier inverting input. See Section 6.3.3 |
| GND | 24 | — | Ground. All signals are referenced to this node. |
| OUTA | 22 | O | 0.2A sink and source primary switching output. |
| OUTB | 21 | O | |
| OUTC | 20 | O | |
| OUTD | 19 | O | |
| OUTE | 18 | O | |
| OUTF | 17 | O | |
| RSUM | 11 | I | Slope compensation programming. Voltage mode or peak current mode setting. See Section 6.3.11 |
| RT | 10 | I | Oscillator frequency set. leader or follower mode setting. See Section 6.3.10 |
| SS/EN | 5 | I | Soft-start programming, device enable and hiccup mode protection circuit. See Section 6.3.4 |
| SYNC | 16 | I/O | Synchronization out from leader controller to input of follower controller. See Section 6.3.15 |
| TMIN | 9 | I | Minimum duty cycle programming in burst mode. See Section 6.3.9 |
| VDD | 23 | I | Bias supply input. See Section 6.3.17 |
| VREF | 1 | O | 5V, ±1.5%, 20mA reference voltage output. See Section 6.3.2 |