The resistor R_EF from the DELEF pin to GND along with the resistor divider R_AEFHI from CS pin to ADELEF pin and R_AEF from ADELEF pin to GND sets equal delays T_AFSET and T_BESET between outputs OUTA or OUTB going low and related output OUTF or OUTE going low Figure 6-4. The total resistance of this resistor divider should be in the range between 10kΩ and 20kΩ.

Figure 6-4 Delay Definitions Between OUTA and OUTF, OUTB and OUTE

These delays gradually increase as function of the CS signal from T_AFSET1, which is measured at V_CS = 0.2V, to T_AFSET2, which is measured at V_CS = 1.8V. This is opposite to the DELAB and DELCD behavior and this delay is longest (T_AFSET2) when the signal at CS pin is maximized and shortest (T_AFSET1) when the CS signal is minimized. This approach will reduce the synchronous rectifier MOSFET body diode conduction time over a wide load current range thus improving efficiency. The ratio between the longest and shortest delays is set by the resistor divider R_AEFHI and R_AEF. If CS and ADELEF are tied, the ratio is maximized. If ADELEF is connected to GND, then the delay is fixed, defined only by resistor R_EF from DELEF to GND.

The delay time T_AFSET is defined by the following Equation 6. Equation 6 also defines the delay time T_BESET.

where

• the CS, which is the voltage at pin CS, is in volts
• K_EF is a numerical gain factor of CS voltage from 0 to 1

Equation 7 is an empirical approximation of measured data, thus, there is no unit agreement in it. As an example, assume R_EF = 15kΩ, CS = 1V and K_EF = 0.5. Then the T_AFSET is going to be 41.7ns. K_EF is defined as Equation 7:

Equation 7.

R_AEF and R_AEFHI define the portion of voltage at pin CS applied to the pin ADELEF (see Figure 7-3). K_EF defines how significantly the delay time depends on CS voltage. K_EF varies from 0, where ADELEF pin is shorted to ground (R_AEF = 0) and the delay does not depend on CS voltage, to 1, where ADELEF is tied to CS (R_AEFHI = 0).

The plots in Figure 6-5 and Figure 6-6 show delay time settings as function of CS voltage and K_EF for two different conditions: R_EF = 13kΩ (Figure 6-5) and R_EF = 90kΩ (Figure 6-6)

Figure 6-5 Delay Time T_AFSET and T_BESET (Over CS Voltage and Selected K_EF for R_EF Equal 13k?)

Figure 6-6 Delay Time T_AFSET and T_BESET (Over CS Voltage and Selected K_EF for R_EF Equal 90k?)