ZHCSBB1D July 2013 – March 2018 UCC28740
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedure
- 8.2.2.1 Custom Design With WEBENCH® Tools
- 8.2.2.2 Standby Power Estimate and No-Load Switching Frequency
- 8.2.2.3 Input Bulk Capacitance and Minimum Bulk Voltage
- 8.2.2.4 Transformer Turns-Ratio, Inductance, Primary Peak Current
- 8.2.2.5 Transformer Parameter Verification
- 8.2.2.6 VS Resistor Divider, Line Compensation
- 8.2.2.7 Output Capacitance
- 8.2.2.8 VDD Capacitance, CVDD
- 8.2.2.9 Feedback Network Biasing
- 8.2.3 Application Curves
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
8.2.2.6 VS Resistor Divider, Line Compensation
The VS divider resistors determine the output overvoltage detection point of the flyback converter. The high-side divider resistor (RS1) determines the input-line voltage at which the controller enables continuous DRV operation. RS1 is determined based on transformer primary-to-auxiliary turns-ratio and desired input voltage operating threshold.
The low-side VS pin resistor is then selected based on the desired overvoltage limit, VOV.
The UCC28740 maintains tight constant-current regulation over varying input line by using the line-compensation feature. The line-compensation resistor (RLC) value is determined by current flowing in RS1 and the total internal gate-drive and external MOSFET turnoff delay. Assume an internal delay of 50 ns in the UCC28740.
