ZHCSBB1D July 2013 – March 2018 UCC28740
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedure
- 8.2.2.1 Custom Design With WEBENCH® Tools
- 8.2.2.2 Standby Power Estimate and No-Load Switching Frequency
- 8.2.2.3 Input Bulk Capacitance and Minimum Bulk Voltage
- 8.2.2.4 Transformer Turns-Ratio, Inductance, Primary Peak Current
- 8.2.2.5 Transformer Parameter Verification
- 8.2.2.6 VS Resistor Divider, Line Compensation
- 8.2.2.7 Output Capacitance
- 8.2.2.8 VDD Capacitance, CVDD
- 8.2.2.9 Feedback Network Biasing
- 8.2.3 Application Curves
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
7.4.2 Primary-Side Constant-Current (CC) Regulation
When the load current of the converter increases to the predetermined constant-current limit, operation enters CC mode. In CC mode, output voltage regulation is lost and the shunt-regulator drives the current and voltage at FB to minimum. During CC mode, timing information at the VS pin and current information at the CS pin allow accurate regulation of the average current of the secondary winding. The CV-regulation control law dictates that as load increases approaches CC regulation the primary peak current will be at IPP(max). The primary peak current, turns-ratio, demagnetization time tDM, and switching period tSW determine the secondary average output current (see Figure 16). Ignoring leakage-inductance effects, the average output current is given by Equation 5. When the demagnetization duty-cycle reaches the CC-regulation reference, DMAGCC, in the current-control block, the controller operates in frequency modulation (FM) mode to control the output current for any output voltage at or below the voltage-regulation target as long as the auxiliary winding keeps VVDD above the UVLO turnoff threshold. As the output voltage falls, tDM increases. The controller acts to increase tSW to maintain the ratio of tDM to switching period (tDM / tSW) at a maximum of 0.425 (DMAGCC), thereby maintaining a constant average output current.
Figure 16. Transformer-Current Relationship
Fast, accurate, opto-coupled CV control combined with line-compensated PSR CC control results in high-performance voltage and current regulation which minimizes voltage deviations due to heavy load and unload steps, as illustrated by the V-I curve in Figure 17.
Figure 17. Typical Target Output V-I Characteristic