ZHCSEQ1A February 2016 – February 2016 UCC28704
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說(shuō)明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Detailed Pin Description
- 7.3.2 Primary-Side Regulation (PSR)
- 7.3.3 Primary-Side Constant Voltage (CV) Regulation
- 7.3.4 Primary-Side Constant Current (CC) Regulation
- 7.3.5 Valley-Switching and Valley-Skipping
- 7.3.6 Start-Up Operation
- 7.3.7 Fault Protection
- 7.3.8 Constant Current Under-Voltage Protection
- 7.3.9 Load Transient Response
- 7.4 Device Functional Modes
-
8 Applications and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedure
- 8.2.2.1 VDD Capacitance, CDD
- 8.2.2.2 VDD Start-Up Resistance, RSTR
- 8.2.2.3 Input Bulk Capacitance and Minimum Bulk Voltage
- 8.2.2.4 Transformer Turns Ratio, Inductance, Primary-Peak Current
- 8.2.2.5 Transformer Parameter Verification
- 8.2.2.6 VS Resistor Divider, Line Compensation, and NTC
- 8.2.2.7 Standby Power Estimate
- 8.2.2.8 Output Capacitance
- 8.2.2.9 Design Considerations in Using with Synchronous Rectifiers
- 8.2.3 Application Curves
- 8.3 Do's and Don'ts
- 9 Power Supply Recommendations
- 10Layout
-
11器件和文檔支持
- 11.1
器件支持
- 11.1.1
器件命名規(guī)則
- 11.1.1.1 電容術(shù)語(yǔ)（以法拉為單位）
- 11.1.1.2 占空比術(shù)語(yǔ)
- 11.1.1.3 頻率術(shù)語(yǔ)（以赫茲為單位）
- 11.1.1.4 電流術(shù)語(yǔ)（以安培為單位）
- 11.1.1.5 電流和電壓調(diào)節(jié)術(shù)語(yǔ)
- 11.1.1.6 變壓器術(shù)語(yǔ)
- 11.1.1.7 功率術(shù)語(yǔ)（以瓦特為單位）
- 11.1.1.8 電阻術(shù)語(yǔ)（以 Ω 為單位）
- 11.1.1.9 時(shí)序術(shù)語(yǔ)（以秒為單位）
- 11.1.1.10 電壓術(shù)語(yǔ)（以伏特為單位）
- 11.1.1.11 交流電壓術(shù)語(yǔ)（以 VRMS 為單位）
- 11.1.1.12 效率術(shù)語(yǔ)
- 11.1.1
器件命名規(guī)則
- 11.2 文檔支持
- 11.3 社區(qū)資源
- 11.4 商標(biāo)
- 11.5 靜電放電警告
- 11.6 Glossary
- 11.1
器件支持
- 12機(jī)械、封裝和可訂購(gòu)信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DBV|6
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購(gòu)信息
10 Layout
10.1 Layout Guidelines
In order to increase the reliability and feasibility of the project it is recommended to adhere to the following guidelines for PCB layout. In Figure 32, a typical 5-V/2-A USB adapter design schematic is shown in Figure 32.
- Minimize stray capacitance on the VS node. Place the voltage sense resistors (RS1 and RS2 in Figure 24) close to the VS pin.
- Arrange the components to minimize the loop areas of the switching currents as much as possible. These areas include such loops as the transformer primary winding current loop (a), the MOSFET gate-drive loop (b), the primary snubber loop (c), the auxiliary winding loop (d) and the secondary output current loop (e). In practice, trade-offs may have to be made. Loops with higher current should be minimized with higher priority. As a rule of thumb, the priority goes from high to low as (a) – (e) – (c) – (d) – (b).
- The RLC resistor location is critical. To avoid any dv/dt induced noise (for example MOSFET drain dv/dt) coupled onto this resistor, it is better to place RLC closer to the controller and avoid nearby the MOSFET.
- To improve thermal performance increase the copper area connected to GND pins.
Figure 32. 10-W, 5-V/2-A USB Adapter Schematics
10.2 Layout Example
Figure 33 demonstrates a 10-W, 5-V/2-A, layout with trade-offs to minimize the loops while effectively placing components and tracks for low noise operation on a single-layer printed circuit board. In addition to the consideration of minimal loops, one another layout guideline is always to use the device GND as reference point. This applies to both power and signal to return to the device GND pin (pin 5).
Figure 33. Layout Example