Table 1. UCC28704 Design Parameters

8.2.2.1 VDD Capacitance, C_DD

The capacitance on VDD needs to supply the device operating current until the output of the converter reaches the target minimum operating voltage. At this time the auxiliary winding can sustain the voltage to the UCC28704. The total output current available to the load and to charge the output capacitors is the constant-current regulation target. The equation below assumes the output current of the flyback is available to charge the output capacitance until the minimum output voltage V_OCC is achieved. The gate-drive current depends on particular MOSFET to be used. If with an estimated 1.0 mA of gate-drive current, C_DD is determined by Equation 9.

Equation 9.

8.2.2.2 VDD Start-Up Resistance, R_STR

Once the VDD capacitance is known, the start-up resistance from V_BULK to achieve the power-on delay time (t_STR) target can be determined.

Equation 10.

8.2.2.3 Input Bulk Capacitance and Minimum Bulk Voltage

Determine the minimum voltage on the input capacitance, C_B1 and C_B2 total, in order to determine the maximum Np to Ns turns ratio of the transformer. The input power of the converter based on target full-load efficiency, minimum input rms voltage, and minimum AC input frequency are used to determine the input capacitance requirement.

Maximum input power is determined based on V_OCV, I_OCC, and the full-load efficiency target. An initial estimate of 84% can be assumed for the full-load efficiency for a 5-V/2-A design.

Equation 11.

Equation 12 provides an accurate solution for input capacitance based on a target minimum bulk capacitor voltage. To target a given input capacitance value, iterate the minimum capacitor voltage to achieve the target capacitance.

Equation 12.

8.2.2.4 Transformer Turns Ratio, Inductance, Primary-Peak Current

The maximum primary-to-secondary turns ratio can be determined by the target maximum switching frequency at full load, the minimum input capacitor bulk voltage, and the estimated DCM resonant time.

Initially determine the maximum available total duty cycle of the on time and secondary conduction time based on target switching frequency and DCM resonant time. For DCM resonant time, assume 500 kHz if you do not have an estimate from previous designs. For the transition mode operation limit, the period required from the end of secondary current conduction to the first valley of the V_DS voltage is ½ of the DCM resonant period, or 1 µs assuming 500-kHz resonant frequency. D_MAX can be determined using Equation 13.

Equation 13.

Once D_MAX is known, the maximum turns ratio of the primary to secondary can be determined with the equation below. D_MAGCC is defined as the secondary diode conduction duty cycle during constant-current, CC, operation. It is set internally by the UCC28704 at 0.475. The total voltage on the secondary winding needs to be determined; which is the sum of V_OCV, the secondary rectifier V_F, and the cable compensation voltage (V_OCBC). For the 5-V USB charger applications, a turns ratio range of 12 to 15 is typically used for a 10-W design.

Equation 14.

N_PS is determined also with other design factors such as primary MOSFET, secondary rectifier diode, as well as secondary MOSFET if synchronous rectifier is used. Once an optimum turns-ratio is determined from a detailed transformer design, use this ratio for the following parameters.

The UCC28704 controller constant-current regulation is achieved by maintaining D_MAGCC = 0.475 at the maximum primary current setting. The transformer turns ratio and constant-current regulating voltage determine the current sense resistor for a target constant current limit.

Since not all of the energy stored in the transformer is transferred to the secondary, a transformer efficiency term is included. This efficiency number includes the core and winding losses, leakage inductance ratio, and bias power ratio to rated output power. For a 5-V, 2-A charger example, bias power of 0.5% is a good estimate. An overall transformer efficiency of 94.5% is a good estimation of assuming 2% leakage inductance, 3% core and winding loss, and 0.5% bias power.

R_CS is used to program the primary-peak current with Equation 15:

Equation 15.

The primary transformer inductance can be calculated using the standard energy storage equation for flyback transformers. Primary current, maximum switching frequency, output and transformer efficiency are included in Equation 16. Initially determine transformer primary current.

Initially the transformer primary current should be determined. Primary current is simply the maximum current sense threshold divided by the current sense resistance.

Equation 16.

Equation 17.

The secondary winding to auxiliary winding transformer turns ratio (N_AS) is determined by the lowest target operating output voltage in constant-current regulation and the VDD UVLO of the UCC28704. There is additional energy supplied to VDD from the transformer leakage inductance energy which allows a lower turns ratio to be used in many designs. The V_OCC lower than CCUV level is not achievable because the CCUV protection is going to be triggered first.

Equation 18.

8.2.2.5 Transformer Parameter Verification

The transformer turns-ratio selected affects the MOSFET V_DS and secondary rectifier reverse voltage so these should be reviewed. The UCC28704 controller requires a minimum on time of the MOSFET (t_ON) and minimum D_MAG time (t_DMAG(min)) of the secondary rectifier in the high line, minimum-load condition. The selection of f_MAX, L_P and R_CS affects the minimum t_ON and t_DMAG.

The secondary rectifier and MOSFET voltage stress can be determined by the equations below.

Equation 19.

For the MOSFET V_DS voltage stress, an estimated leakage inductance voltage spike (V_LK) needs to be included.

Equation 20.

The following equations are used to determine for the minimum t_ON target of 0.3 µs and minimum de-mag time, t_DMAG(min), target of 1.7 µs. The minimum t_DMAG(min) target needs to be typically 2.45 µs when a synchronous rectifier is used on the secondary-side instead of a Schottky diode rectifier. Additional details are provided in Design Considerations in Using with Synchronous Rectifiers.

Equation 21.

Equation 22.

8.2.2.6 VS Resistor Divider, Line Compensation, and NTC

The VS divider resistors determine the output voltage regulation point of the flyback converter, also the high-side divider resistor (R_S1) determines the line voltage at which the controller enables continuous DRV operation. R_S1 is initially determined based on the transformer auxiliary to primary turns-ratio and the desired input voltage operating threshold.

Equation 23.

The low-side VS pin resistor is selected based on desired V_O regulation voltage. I_VSL(run) is VS pin run current with a typical value 220 µA for a design.

Equation 24.

The UCC28704 can maintain tight constant-current regulation over input line by utilizing the line compensation feature. The line compensation resistor (R_LC) value is determined by current flowing in R_S1 and expected gate drive and MOSFET turn-off delay. Assume a 50-ns internal delay in the UCC28704.

Equation 25.

The NTC function on NTC/SU-pin is to program with a NTC resistor for the desired over-temperature shutdown threshold. The shut-down threshold is 0.95 V with an internal 105-μA current source which results in a 9.05-kΩ thermistor shut-down threshold. The SU function on NTC/SU-pin is described in Initial Power-On with A Depletion-Mode FET. Pulling down this pin to GND stops switching and can be used for remote enable and disable control. This pin should be left floating if not used.

8.2.2.7 Standby Power Estimate

Assuming no-load standby power is a critical design parameter, determine the estimated no-load power based on target converter maximum switching frequency and output power rating. The following equation estimates the stand-by power of the converter.

Equation 26.

For a typical USB charger application, the bias power during no-load is approximately 2.1 mW. This is based on 21-V VDD and 100-µA bias current. The output preload resistor can be estimated by V_OCV and the difference in the converter stand-by power and the bias power. The equation for output preload resistance accounts for bias power estimated at 2.1 mW. Preload resistor value is estimated in Equation 27 :

Equation 27.

Typical start-up resistance values for R_STR range from 10 MΩ to 15 MΩ to achieve less than 2-s start-up time. The capacitor bulk voltage for the loss estimation is the highest voltage for the stand-by power measurement, typically 325 V_DC.

Equation 28.

For the total stand-by power estimation add an estimated 2.5 mW for snubber loss to the start-up resistance and converter stand-by power loss.

Equation 29.

8.2.2.8 Output Capacitance

The output capacitance value is typically determined by the transient response requirement from no-load. For example, in some USB charger applications there is a requirement to maintain a minimum V_O of 4.1 V with a load-step transient of 0 mA to 500 mA . Equation 30 assumes that the switching frequency can be at the UCC28704 minimum of f_SW(min).

Equation 30.

Equation 5 should be observed together with Equation 30 for stability consideration when determine C_OUT.

Another consideration of the output capacitor(s) is the ripple voltage requirement. The output capacitors and their total ESR are the main factors to determine the output voltage ripple. Equation 31 provides a formula to determine required ESR value R_ESR, and Equation 31 provides a formula to determine required capacitance. The total output ripple is the sum of these two parts with scale factors and 10mV to consider other noise as shown in Equation 33,

Equation 31.

Equation 32.

Equation 33.

Example: if require V_RIPPLE = 70 mV, assume 0.81 × V_{RIPPLE_R} = 1.15 × V_{RIPPLE_C} = 30 mV, then R_ESR = 4.05 mΩ, and C_OUT = 643 µF, with assumption of L_P = 700 µH, I_PP(max) = 0.713 A, N_PS = 13, V_OCV = 5 V, V_CBC = 0.3 V.

8.2.2.9 Design Considerations in Using with Synchronous Rectifiers

Special design considerations need to be observed when using synchronous rectifiers (SR) with the UCC28704. Figure 14 depicts the de-mag time partition. When using UCC28704 with SR, a portion of the de-mag time needs to be reserved for t_bw, as shown in Figure 25, which is the body diode conduction time when SR MOSFET turns off before the de-mag time ends.

Figure 25. Auxiliary Waveform Details

The critical parameter dictating the maximum switching frequency when UCC28704 is used with an SR is determined based on t_DMAG(min). The t_DMAG(min) needs to be typically 2.45 µs including the SR bump width (t_BW) is 750 ns. The 750-ns (t_BW) is required for the internal circuit to filter out the SR bump change caused by MOSFET body diode conduction that is sensed on the VS pin waveform. The corresponding switching frequency measured at starting point of constant current operation should not be greater than 55 kHz.