The power losses of the UCC2773x-Q1 (P_UCC2773x-Q1) are estimated by calculating losses from several components.The combined power losses due to quiescent current (I_QDD, I_QBS) and no-load switching are calculated below:

Refer to Figure 5-16 to find I_VDD and I_VHB. Static losses due to leakage current (I_BL) are calculated from the HB high-voltage node as shown below:

Note that static losses due to I_BLincrease with temperature. See Figure 5-10.

Dynamic losses incurred due to the gate charge while driving the FETs Q1 and Q2 are calculated below. Please note that this component typically dominates over the dynamic losses related to the internal VDD and VHB switching logic circuitry in the UCC2773x-Q1.

The dynamic losses are shared between the internal pullup and pulldown resistance of the gate driver IC, the external gate resistance, and the internal gate resistance of the switching device. The pullup resistance changes dynamically during switching, so using R_OH provides for an overestimate of the gate driver power dissipation, which provides for design margin.

The total power losses in the gate driver IC for this example are calculated below: