SLUSFS4A September 2025 – September 2025 UCC27734-Q1 , UCC27735-Q1
PRODUCTION DATA
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Pin Configuration and Functions
- 5 Specifications
-
6 Detailed Description
- 6.1 Overview
- 6.2 Functional Block Diagram
- 6.3
Feature Description
- 6.3.1 Input Stages and Interlock
- 6.3.2 Enable Function (UCC277x5-Q1 Only)
- 6.3.3 Undervoltage Lockout (UVLO)
- 6.3.4 Level Shifter
- 6.3.5 Output Stage
- 6.3.6 Low Propagation Delays and Tightly Matched Outputs
- 6.3.7 HS Node dV/dt
- 6.3.8 Split Grounds (COM and VSS)
- 6.3.9 Operation Under Negative HS Voltage Condition
- 6.4 Device Functional Modes
-
7 Application and Implementation
- 7.1 Application Information
- 7.2
Typical Application
- 7.2.1 Design Requirements
- 7.2.2
Detailed Design Procedure
- 7.2.2.1 Selecting HI and LI Low Pass Filter Components (RHI, RLI, CHI, CLI)
- 7.2.2.2 Selecting Bootstrap Capacitor (CBOOT)
- 7.2.2.3 Selecting VDD Bypass Capacitor (CVDD)
- 7.2.2.4 Selecting Bootstrap Resistor (RBOOT)
- 7.2.2.5 Selecting Gate Resistor RHO/RLO
- 7.2.2.6 Selecting Bootstrap Diode
- 7.2.2.7 Estimate the UCC2773x-Q1 Power Losses
- 7.2.2.8 Application Example Schematic Note
- 7.2.3 Application Curves
- 7.3 Power Supply Recommendations
- 7.4 Layout
- 8 Device and Documentation Support
- 9 Revision History
- 10Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- D|8
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購(gòu)信息
8.5 Electrostatic Discharge Caution
 |
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. |
| ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. |