4 Pin Configuration and Functions

UCC27302A-Q1 DDA Package8-Pin SOIC with PowerPad?Top
View

Figure 4-1 DDA Package8-Pin SOIC with PowerPad?Top View

UCC27302A-Q1 DRC Package10-Pin SONTop View

Figure 4-3 DRC Package10-Pin SONTop View

UCC27302A-Q1 D Package8-Pin SOICTop View

Figure 4-2 D Package8-Pin SOICTop View

Table 4-1 Pin Functions

PIN				TYPE⁽³⁾	DESCRIPTION
NAME	D	DDA	DRC	TYPE⁽³⁾	DESCRIPTION
EN	N/A	N/A	6	I	Enable input. When this pin is pulled high, it will enable the driver. If left floating or pulled low, it will disable the driver. A filter capacitor, typically 1-10nF, is recommended to be placed from EN to VSS to increase noise immunity in sensitive applications.
HB	2	2	3	P	High-side bootstrap supply. The bootstrap diode is on-chip but the external bootstrap capacitor is required. Connect positive side of the bootstrap capacitor to this pin. Typical range of HB bypass capacitor is 0.022μF to 0.1μF. The capacitor value is dependant on the gate charge of the high-side MOSFET and must also be selected based on speed and ripple criteria.
HI	5	5	7	I	High-side input.⁽¹⁾
HO	3	3	4	O	High-side output. Connect to the gate of the high-side power MOSFET.
HS	4	4	5	P	High-side source connection. Connect to source of high-side power MOSFET. Connect the negative side of bootstrap capacitor to this pin.
LI	6	6	8	I	Low-side input.⁽¹⁾
LO	8	8	10	O	Low-side output. Connect to the gate of the low-side power MOSFET.
VDD	1	1	1	P	Positive supply to the lower-gate driver. Decouple this pin to V_SS (GND). Typical decoupling capacitor range is 0.22μF to 4.7μF (see ⁽²⁾).
VSS	7	7	9	G	Negative supply terminal for the device that is generally grounded.
Thermal pad⁽⁴⁾	—	Pad	Pad	—	Connect to a large thermal mass trace and GND plane to dramatically improve thermal performance.

(1) HI, LI, and EN inputs are assumed to connect to a low impedance source signal (100Ω). If the source impedance is greater than 100Ω, add a bypassing capacitor, each, between HI to VSS, LI to VSS, and EN to VSS. The added capacitor value depends on the noise levels presented on the pins, typically from 1nF to 10nF should be effective to eliminate the possible noise effect. When noise is present on two pins, HI or LI, the effect is to cause HO and LO malfunctions to have wrong logic outputs.

(2) For cold temperature applications TI recommends the upper capacitance range. Follow the Layout Guidelines for PCB layout.

(3) G = Ground, I = Input, O = Output, and P = Power.

(4) Pin VSS and the exposed thermal pad are internally connected on the DRC package only. On the DDA package, the thermal pad is not directly connected to any leads of the package; however, it is electrically and thermally connected to the substrate which is the ground of the device.