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ZHCSHQ7B February 2018 – April 2024 UCC21222-Q1

PRODUCTION DATA

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

D|16
- MPDS178G

散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購(gòu)信息

5.8 Electrical Characteristics

V_VCCI = 3.3 V or 5.0 V, 0.1-μF capacitance from VCCI to GND, V_VDDx = 12V (for 8V UVLO), , 1-μF + 100-nF capacitance from VDDA and VDDB to VSSA and VSSB, DT pin floating, EN = VCC or DIS = GND, T_J = –40°C to +150°C, C_L = 0 pF, unless otherwise noted ⁽¹⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY CURRENTS
I_VCC	VCC quiescent current	V_INx = 0 V, EN = VCC; VCC=3.3V		1.4	2	mA
		V_INx = 0 V, EN = VCC; VCC=5V		1.4	2
		V_INx = VCC, EN = VCC; VCC=3.3V		4.2	4.8
		V_INx = VCC, EN = VCC; VCC=5V		4.2	4.8
		V_INxPWM at 0V to VCC at f_SW = 500kHz, EN = VCC; VCC=3.3V		2.7	3.2
		V_INxPWM at 0V to VCC at f_SW = 500kHz, EN = VCC; VCC=5V		2.7	3.2
I_VDDx	VDDx quiescent current	V_INx = 0 V, EN = VCC;		1.2	2	mA
		V_INx = 0 V, EN = VCC; VDD=25V		1.4	2.3
		V_INx = VCC, EN = VCC;		1.4	2.2
		V_INx = VCC, EN = VCC; VDD=25V		1.5	2.5
		V_INxPWM at 0V to VCC at f_SW = 500kHz, EN = VCC;		2.7	4.4
		V_INxPWM at 0V to VCC at f_SW = 500kHz, EN = VCC; VDD=25V		2.7	4.4
VCC SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS
V_{VCC_ON}	VCC UVLO Rising Threshold		2.55	2.7	2.85	V
V_{VCC_OFF}	VCC UVLO Falling Threshold		2.35	2.5	2.65
V_{VCC_HYS}	VCC UVLO Threshold Hysteresis			0.2
t_{VCC+ to OUT}	VCC UVLO ON Delay		18	42	80	μs
t_{VCC– to OUT}	VCC UVLO OFF Delay		0.5	1.2	7
t_VCCFIL	VCC UVLO Deglitch Filter		0.4	0.9	3.1
VDD SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS AND DELAY
V_{VDD_ON}	VDDx UVLO Rising Threshold	8-V UVLO Option	7.7	8.5	8.9	V
V_{VDD_OFF}	VDDx UVLO Falling Threshold		7.2	7.9	8.4
V_{VDD_HYS}	VDDx UVLO Threshold Hysteresis			0.6
t_{VDD+ to OUT}	VDDx UVLO ON Delay				10	μs
t_{VDD– to OUT}	VDDx UVLO OFF Delay		0.1	0.5	2
t_VDDFIL	VDDx UVLO Deglitch Filter		0.1	0.17
INA, INB, AND /DIS
V_{INx_H}, V_{DIS_H}_,	Input High Threshold Voltage			2	2.3	V
V_{INx_L}, V_{DIS_L}_,	Input Low Threshold Voltage		0.8	1
V_{INx_HYS}, V_{DIS_HYS}_,	Input Threshold Hysteresis			1
R_INxD	INx Pin Pull Down Resistance	INx = 3.3V	50	90	185	kΩ
R_DISD	DIS Pin Pull Up Resistance	DIS= 3.3V	50	90	185	kΩ
OUTPUT DRIVER STAGE
I_O+	Peak Output Source Current	C_VDDx = 10 μF, C_L = 0.22 μF, f = 1 kHz		–4		A
I_O–	Peak Output Sink Current	C_VDDx = 10 μF, C_L = 0.22 μF, f = 1 kHz		6		A
R_OH	Pull up resistance. R_OHdoes not represent drive pull-up performance. See Section 8.3.4 for details.	I_OUTx = –0.05A		5		?
R_OL	Pull down resistance	I_OUTx = 0.05A		0.55		?
ACTIVE PULL-DOWN
V_OUTPD	Output Active Pull Down on OUTx	I_OUT = 200mA, VDDx floating and unpowered.		1.6	2	V
V_OUTPD	Output Active Pull Down on OUTx	I_OUT = 200mA, C_VDD=100nF and unpowered.		1.6	2	V
DEADTIME AND OVERLAP PROGRAMMING
DT_S	Disable DT Function	DT pin open or pull DT pin to VCC	Output overlapping determined by INA, INB			-
	Deadtime Programming for R_DT≤0.15k?	R_DT=0~0.15k?	-6	0.2	6	ns
	Deadtime Programming for 1.7k?≤R_DT≤100k? DT (ns) = 8.6×R_DT(k?) + 13	R_DT = 10 kΩ	86	99	112	ns
		R_DT = 20 kΩ	167	185	203
		R_DT = 50 kΩ	399	443	487

(1) Current direction in the testing conditions are defined to be positive into the pin and negative out of the specified terminal (unless
otherwise noted)