ZHCSHQ7B February 2018 – April 2024 UCC21222-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Pin Configuration and Functions
-
5 Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 ESD Ratings (Automotive)
- 5.3 Recommended Operating Conditions
- 5.4 Thermal Information
- 5.5 Power Ratings
- 5.6 Insulation Specifications
- 5.7 Safety Limiting Values
- 5.8 Electrical Characteristics
- 5.9 Switching Characteristics
- 5.10 Insulation Characteristics Curves
- 5.11 Typical Characteristics
- 6 Parameter Measurement Information
- 7 Detailed Description
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedure
- 8.2.2.1 Custom Design With WEBENCH? Tools
- 8.2.2.2 Designing INA/INB Input Filter
- 8.2.2.3 Select Dead Time Resistor and Capacitor
- 8.2.2.4 Select External Bootstrap Diode and its Series Resistor
- 8.2.2.5 Gate Driver Output Resistor
- 8.2.2.6 Estimating Gate Driver Power Loss
- 8.2.2.7 Estimating Junction Temperature
- 8.2.2.8 Selecting VCCI, VDDA/B Capacitor
- 8.2.2.9 Application Circuits with Output Stage Negative Bias
- 8.2.3 Application Curves
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Revision History
- 13Mechanical, Packaging, and Orderable Information
6.6 Power-Up UVLO Delay to OUTPUT
Before the driver is ready to deliver a proper output state, there is a power-up delay from the UVLO rising edge to output and it is defined as tVCCI+ to OUT for VCCI UVLO (typically 40us) and tVDD+ to OUT for VDD UVLO (typically 5us). It is recommended to consider proper margin before launching PWM signal after the driver's VCCI and VDD bias supply is ready. Figure 6-7 and Figure 6-8 show the power-up UVLO delay timing diagram for VCCI and VDD.
If INA or INB are active before VCCI or VDD have crossed above their respective on thresholds, the output will not update until tVCCI+ to OUT or tVDDx+ to OUT after VCCI or VDD crossing its UVLO rising threshold. However, when either VCCI or VDD receive a voltage less than their respective off thresholds, there is <2μs delay, depending on the voltage slew rate on the supply pins, before the outputs are held low. This asymmetric delay is designed to ensure safe operation during VCCI or VDD brownouts.
Figure 6-7 VCCI
Power-Up UVLO Delay
Figure 6-8 VDDA/B
Power-Up UVLO Delay