13 Revision History

Changes from Revision F (February 2024) to Revision G (November 2024)

• 更新了“特性”部分以反映器件特性Go
• 將 CMTI 從大于 100V/ns 更改為大于 125V/nsGo
• 將傳播延遲從 40ns 最大值更改為 33ns 典型值Go
• 刪除了關于最大延遲匹配的要點Go
• 將最大脈寬失真從 5.5ns 更改為 5nsGo
• 將 VDD 上電延遲最大值從 35us 更改為 10usGo
• 將最大 VDD 輸出驅動電源電壓從 18V 更改為 25VGo
• 將工作溫度范圍更改為結溫范圍Go
• 刪除了關于抑制短于 5ns 的輸入脈沖的要點Go
• 將認證更新為最新標準Go
• 將 CMTI 從大于 100V/ns 更改為大于 125V/nsGo
• 刪除了有關抑制短瞬變的輸入和耐受電壓尖峰的輸入/輸出的句子Go
• 將有源下拉電阻從 2.1V 最大值更改為 2V 最大值Go
• Changed 5V UVLO recommended VDD supply minimum from 6V to 6.5VGo
• Changed DIS pin description; leaving DIS pin open would disable the deviceGo
• Changed VDDA-VSSA and VDDB-VSSB absmax from 20V to 30VGo
• Changed all -0.5V minimum to -0.3V to keep consistent with newly released datasheetsGo
• Changed all absolute maximum value from supply+0.5V to supply+0.3V to keep consistent with newly released datasheetsGo
• Deleted input signal voltage transient specGo
• Updated ESD spec from HBM = ±4000 and CDM = ±1500 to HBM = ±2000 and CDM = ±1000 to match ESD industry standardsGo
• Changed VDDA-VSSA and VDDB-VSSB recommended max from 18V to 25VGo
• Changed 5V-UVLO recommended minimum VDDA/B voltage from 6V to 6.5VGo
• Deleted ambient temperature specGo
• Changed junction temperature max from 130°C to 150°CGo
• Updated thermal values from RθJA = 68.5°C/W, RθJC(top) = 30.5°C/W, RθJB = 22.8°C/W, ψJT = 17.1°C/W, ψJB = 22.5°C/W to RθJA = 80.2°C/W, RθJC(top) = 36.6°C/W, RθJB = 45°C/W, ψJT = 28°C/W, ψJB = 44.3°C/WGo
• Updated values from PD = 1825mW, PDI = 15mW, PDA/PDB = 905mW to PD = 950mW, PDI = 50mW, PDA/PDB = 450mW. Changed test conditions. Go
• Updated DIN EN IEC to the latest standard, updated insulation voltage valuesGo
• Updated barrier capacitance valueGo
• Deleted safety-related certifications section, certification ongoingGo
• Changed IS testing condition. Changed IS value from 75mA (with VDDA/B=12V) to 50mA (with VDDA/B=15V) and 30mA (with VDDA/B=25V). Go
• Updated safety-limiting values from PS = 15mW/905mW/905mW/1825mW to PS = 50mW/750mW/750mW/1550mW Go
• Updated IVCCI quiescent current spec Typ value from 1.5mA to 1.4mAGo
• Updated IVDDA/IVDDB quiescent current spec Typ from 1.0mA to 1.2mA and Max value from 1.8mA to 2.0mAGo
• Updated IVCCI operating current Typ value from 2.5mA to 2.7mA and added Max value 3.2mAGo
• Updated IVDDA/IVDDB operating current Typ value from 2.5mA to 2.7mA and added Max value 4.4mA. Deleted Cload from test condition. Go
• Updated values from Rising threshold Min = 5.0V, Typ = 5.5V, Max = 5.9V to Min = 5.7V, Typ = 6.0V, Max = 6.3V Go
• Updated values from Falling threshold Min = 4.7V, Typ = 5.2V, Max = 5.6V to Min = 5.4V, Typ = 5.7V, Max = 6.0V Go
• Updated values from Rising threshold Min = 8V, Typ = 8.5V, Max = 9V to Min = 7.7V, Typ = 8.5V, Max = 8.9V Go
• Updated values from Falling threshold Min = 7.5V, Typ = 8V, Max = 8.5V to Min = 7.2V, Typ = 7.9V, Max = 8.4V Go
• Updated 8-V UVLO hysteresis typ = 0.5V to 0.6VGo
• Updated Input high threshold Typ = 1.8V, Max = 2V to Typ = 2V, Max = 2.3V. Deleted Min specGo
• Deleted Input low threshold voltage Max specGo
• Updated Input threshold hysteresis Typ = 0.8V to Typ = 1VGo
• Updated peak current test condition to 0.22uF load capacitance. Changed peak output source current directionGo
• Updated output resistance test condition from ±10mA to ±5mAGo
• Deleted output voltage at high/low state specsGo
• Updated active pull-down Typ = 1.75V, Max = 2.1V to Typ = 1.6V, Max = 2VGo
• Changed output rise time Typ from 5ns to 8ns. Deleted Max valueGo
• Changed output fall time Typ from 6ns to 8ns. Deleted Max valueGo
• Changed minimum pulse width from Typ = 10ns, Max = 20ns to Min = 4ns, Typ = 12ns, Max = 30nsGo
• Changed propagation delay TPDHL and TPDLH from Typ=28ns, Max = 40ns to Min = 26ns, Typ = 33ns, Max = 45nsGo
• Changed pulse width distortion max from 5.5ns to 5nsGo
• Changed propagation delay matching from Max = 5ns to Max = 6.5ns from TJ = -40C to -10C and Max = 5ns from TJ = -10C to 150CGo
• Changed VCCI power-up delay from Typ = 40us, Max = 59us to Min = 18us, Typ = 42us, Max = 80usGo
• Deleted VDD power up delay Typ 22us and changed Max from 35us to 10usGo
• Updated CMTI from Min = 100V/ns to 125V/nsGo
• Updated thermal curves to match updated characteristicsGo
• Updated typical char plots to show device characteristics Go
• Deleted language on deglitch filter. Changed minimum pulse width from typical 10ns to 12nsGo
• Updated UVLO delay to match new specsGo
• Updated functional block diagram to reflect device characteristicsGo
• Changed logic table; leaving DIS pin open disables the driverGo
• Updated input stage section to match new specsGo
• Added paragraph on minimum pulse width to Output Stage sectionGo
• Updated ESD structure diagram to reflect device characteristicsGo
• Updated device operation mode when DIS is floating. Added recommendation of bypass capacitorGo
• Changed maximum VDDA/VDDB from 18V to 25VGo