ZHCSH68G November 2017 – November 2024 UCC21220 , UCC21220A
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Device Comparison Table
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
- 8 Detailed Description
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1 Design Requirements
- 9.2.2
Detailed Design Procedure
- 9.2.2.1 Designing INA/INB Input Filter
- 9.2.2.2 Select External Bootstrap Diode and its Series Resistor
- 9.2.2.3 Gate Driver Output Resistor
- 9.2.2.4 Estimating Gate Driver Power Loss
- 9.2.2.5 Estimating Junction Temperature
- 9.2.2.6 Selecting VCCI, VDDA/B Capacitor
- 9.2.2.7 Application Circuits with Output Stage Negative Bias
- 9.2.3 Application Curves
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Revision History
- 14Mechanical, Packaging, and Orderable Information
7.5 Power-up UVLO Delay to OUTPUT
Before the driver is ready to deliver a proper output state, there is a power-up delay from the UVLO rising edge to output and it is defined as tVCCI+ to OUT for VCCI UVLO, which is 42 μs typically, and tVDD+ to OUT for VDD UVLO, which is 10 μs maximum. It is recommended to consider proper margin before launching PWM signal after the driver VCCI and VDD bias supply is ready. Figure 7-6 and Figure 7-7 show the power-up UVLO delay timing diagram for VCCI and VDD.
If INA or INB are active before VCCI or VDD have crossed above their respective on thresholds, the output will not update until tVCCI+ to OUT or tVDD+ to OUT after VCCI or VDD crossing its UVLO rising threshold. However, when either VCCI or VDD receive a voltage less than their respective off thresholds, there is <2μs delay, depending on the voltage slew rate on the supply pins, before the outputs are held low. This asymmetric delay is designed to ensure safe operation during VCCI or VDD brownouts.
Figure 7-6 VCCI Power-up UVLO
Delay
Figure 7-7 VDDA/B Power-up UVLO
Delay